From 28ee4fdf20dd4f938036a7de1ca134ff6ebd9da5 Mon Sep 17 00:00:00 2001 From: Akira Hatanaka Date: Thu, 31 May 2012 02:59:44 +0000 Subject: Cleanup and factoring of mips16 tablegen classes. Make register classes CPU16RegsRegClass and CPURARegRegClass available. Add definition of mips16 jalr instruction. Patch by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157730 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/Mips16InstrInfo.td | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) (limited to 'lib/Target/Mips/Mips16InstrInfo.td') diff --git a/lib/Target/Mips/Mips16InstrInfo.td b/lib/Target/Mips/Mips16InstrInfo.td index 7cbf2d4d42..fc530939ed 100644 --- a/lib/Target/Mips/Mips16InstrInfo.td +++ b/lib/Target/Mips/Mips16InstrInfo.td @@ -12,7 +12,23 @@ //===----------------------------------------------------------------------===// let isReturn=1, isTerminator=1, hasDelaySlot=1, isCodeGenOnly=1, - isBarrier=1, hasCtrlDep=1, rx=0b000, ry=0b001 in -def RET16 : FRR16 <0, (outs), (ins CPURAReg:$target), - "jr\t$target", [(MipsRet CPURAReg:$target)], IIBranch>, - Requires<[InMips16Mode]>; + isBarrier=1, hasCtrlDep=1, rx=0, nd=0, l=0, ra=0 in +def RET16 : FRR16_JALRC < (outs), (ins CPURAReg:$target), + "jr\t$target", [(MipsRet CPURAReg:$target)], IIBranch>; + +// As stack alignment is always done with addiu, we need a 16-bit immediate +let Defs = [SP], Uses = [SP] in { +def ADJCALLSTACKDOWN16 : MipsPseudo16<(outs), (ins uimm16:$amt), + "!ADJCALLSTACKDOWN $amt", + [(callseq_start timm:$amt)]>; +def ADJCALLSTACKUP16 : MipsPseudo16<(outs), (ins uimm16:$amt1, uimm16:$amt2), + "!ADJCALLSTACKUP $amt1", + [(callseq_end timm:$amt1, timm:$amt2)]>; +} + + +// Jump and Link (Call) +let isCall=1, hasDelaySlot=1, nd=0, l=0, ra=0 in +def JumpLinkReg16: + FRR16_JALRC<(outs), (ins CPU16Regs:$rs, variable_ops), + "jalr \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>; -- cgit v1.2.3