From 41e632d9e1a55d36cb08b0551ad82a13d9137a5e Mon Sep 17 00:00:00 2001 From: Bill Wendling Date: Fri, 7 Jun 2013 07:04:14 +0000 Subject: Don't cache the instruction and register info from the TargetMachine, because the internals of TargetMachine could change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183493 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/Mips16RegisterInfo.h | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'lib/Target/Mips/Mips16RegisterInfo.h') diff --git a/lib/Target/Mips/Mips16RegisterInfo.h b/lib/Target/Mips/Mips16RegisterInfo.h index 2b3d2b1a4e..13e82a3ffb 100644 --- a/lib/Target/Mips/Mips16RegisterInfo.h +++ b/lib/Target/Mips/Mips16RegisterInfo.h @@ -20,10 +20,8 @@ namespace llvm { class Mips16InstrInfo; class Mips16RegisterInfo : public MipsRegisterInfo { - const Mips16InstrInfo &TII; public: - Mips16RegisterInfo(const MipsSubtarget &Subtarget, - const Mips16InstrInfo &TII); + Mips16RegisterInfo(const MipsSubtarget &Subtarget); bool requiresRegisterScavenging(const MachineFunction &MF) const; -- cgit v1.2.3