From fc2427bcf8703bbf84787e2b42aac0ef11962d2a Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Tue, 13 May 2014 11:17:46 +0000 Subject: [mips] Free up two values in SubtargetFeatureFlag by folding the redundant IsGP32/IsGP64 into IsGP32bit/IsGP64bit Summary: We are currently very close to the 32-bit limit of the current assembler implementation. This is because there is no way to represent an instruction that is available in, for example, Mips3 or Mips32. We have to define a feature bit that represents this. This patch cleans up a pair of redundant feature bits and slightly postpones the point we will reach the limit. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3703 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208685 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/Mips64InstrInfo.td | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'lib/Target/Mips/Mips64InstrInfo.td') diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index 12c6e087c5..df49aa8e78 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -429,7 +429,7 @@ def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>; //===----------------------------------------------------------------------===// def : MipsInstAlias<"move $dst, $src", (DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64), 1>, - Requires<[IsGP64]>; + GPR_64; def : MipsInstAlias<"daddu $rs, $rt, $imm", (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm), 0>; -- cgit v1.2.3