From 36b0fd51de0c2883e5e715287691a2f3d9623c05 Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Fri, 23 May 2014 13:18:02 +0000 Subject: [mips][mips64r6] [ls][dw][lr] are not available in MIPS32r6/MIPS64r6 Summary: Instead the system is required to provide some means of handling unaligned load/store without special instructions. Options include full hardware support, full trap-and-emulate, and hybrids such as hardware support within a cache line and trap-and-emulate for multi-line accesses. MipsSETargetLowering::allowsUnalignedMemoryAccesses() has been configured to assume that unaligned accesses are 'fast' on the basis that I expect few hardware implementations will opt for pure-software handling of unaligned accesses. The ones that do handle it purely in software can override this. mips64-load-store-left-right.ll has been merged into load-store-left-right.ll The stricter testing revealed a Bits!=Bytes bug in passByValArg(). This has been fixed and the variables renamed to clarify the units they hold. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3872 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209512 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/Mips64r6InstrInfo.td | 1 - 1 file changed, 1 deletion(-) (limited to 'lib/Target/Mips/Mips64r6InstrInfo.td') diff --git a/lib/Target/Mips/Mips64r6InstrInfo.td b/lib/Target/Mips/Mips64r6InstrInfo.td index 2e87a60a1e..f971218779 100644 --- a/lib/Target/Mips/Mips64r6InstrInfo.td +++ b/lib/Target/Mips/Mips64r6InstrInfo.td @@ -17,7 +17,6 @@ // Removed: daddi // Removed: ddiv, ddivu, dmult, dmultu // Removed: div, divu -// Removed: ldl, ldr, ldle, ldre, sdl, sdr, sdle, sdre //===----------------------------------------------------------------------===// // -- cgit v1.2.3