From b2930b92d3e9734ced6679844666799648ebbd7a Mon Sep 17 00:00:00 2001 From: Akira Hatanaka Date: Thu, 1 Mar 2012 22:27:29 +0000 Subject: Changes for migrating to using register mask operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151847 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsCallingConv.td | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'lib/Target/Mips/MipsCallingConv.td') diff --git a/lib/Target/Mips/MipsCallingConv.td b/lib/Target/Mips/MipsCallingConv.td index 99f5450c6c..4b7e1d3766 100644 --- a/lib/Target/Mips/MipsCallingConv.td +++ b/lib/Target/Mips/MipsCallingConv.td @@ -160,3 +160,20 @@ def RetCC_Mips : CallingConv<[ CCIfSubtarget<"isABI_N64()", CCDelegateTo>, CCDelegateTo ]>; + +//===----------------------------------------------------------------------===// +// Callee-saved register lists. +//===----------------------------------------------------------------------===// + +def CSR_SingleFloatOnly : CalleeSavedRegs<(add (sequence "F%u", 31, 20), RA, FP, + (sequence "S%u", 7, 0))>; + +def CSR_O32 : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP, + (sequence "S%u", 7, 0))>; + +def CSR_N32 : CalleeSavedRegs<(add D31_64, D29_64, D27_64, D25_64, D24_64, + D23_64, D22_64, D21_64, RA_64, FP_64, GP_64, + (sequence "S%u_64", 7, 0))>; + +def CSR_N64 : CalleeSavedRegs<(add (sequence "D%u_64", 31, 24), RA_64, FP_64, + GP_64, (sequence "S%u_64", 7, 0))>; -- cgit v1.2.3