From cb39aa05afd52f017869ce5399652223626da7b7 Mon Sep 17 00:00:00 2001 From: Akira Hatanaka Date: Thu, 27 Sep 2012 19:09:21 +0000 Subject: MIPS DSP: ABSQ_S.PH instruction sub-class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164787 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsDSPInstrFormats.td | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'lib/Target/Mips/MipsDSPInstrFormats.td') diff --git a/lib/Target/Mips/MipsDSPInstrFormats.td b/lib/Target/Mips/MipsDSPInstrFormats.td index b01da9bfa1..450d021fa2 100644 --- a/lib/Target/Mips/MipsDSPInstrFormats.td +++ b/lib/Target/Mips/MipsDSPInstrFormats.td @@ -99,6 +99,33 @@ class PRECR_SRA_PH_W_FMT op> : DSPInst { let Inst{5-0} = 0b010001; } +// ABSQ_S.PH sub-class format. +class ABSQ_S_PH_R2_FMT op> : DSPInst { + bits<5> rd; + bits<5> rt; + + let Opcode = SPECIAL3_OPCODE.V; + + let Inst{25-21} = 0; + let Inst{20-16} = rt; + let Inst{15-11} = rd; + let Inst{10-6} = op; + let Inst{5-0} = 0b010010; +} + + +class REPL_FMT op> : DSPInst { + bits<5> rd; + bits<10> imm; + + let Opcode = SPECIAL3_OPCODE.V; + + let Inst{25-16} = imm; + let Inst{15-11} = rd; + let Inst{10-6} = op; + let Inst{5-0} = 0b010010; +} + // SHLL.QB sub-class format. class SHLL_QB_FMT op> : DSPInst { bits<5> rd; -- cgit v1.2.3