From 54c5bc87992ebeaa9e71f2bfb60ac5cf74b77db3 Mon Sep 17 00:00:00 2001 From: Akira Hatanaka Date: Thu, 21 Jun 2012 20:39:10 +0000 Subject: 1. fix null program output after some other changes 2. re-enable null.ll test 3. fix some minor style violations Patch by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158935 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsISelDAGToDAG.cpp | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'lib/Target/Mips/MipsISelDAGToDAG.cpp') diff --git a/lib/Target/Mips/MipsISelDAGToDAG.cpp b/lib/Target/Mips/MipsISelDAGToDAG.cpp index 4236f74dea..15e745f7ea 100644 --- a/lib/Target/Mips/MipsISelDAGToDAG.cpp +++ b/lib/Target/Mips/MipsISelDAGToDAG.cpp @@ -125,7 +125,10 @@ void MipsDAGToDAGISel::InitGlobalBaseReg(MachineFunction &MF) { const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc(); unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg(); - int FI = MipsFI->initGlobalRegFI(); + int FI; // should initialize this to some kind of null + + if (!Subtarget.inMips16Mode()) + FI= MipsFI->initGlobalRegFI(); const TargetRegisterClass *RC = Subtarget.isABI_N64() ? (const TargetRegisterClass*)&Mips::CPU64RegsRegClass : @@ -187,6 +190,10 @@ void MipsDAGToDAGISel::InitGlobalBaseReg(MachineFunction &MF) { assert(Subtarget.isABI_O32()); + if (Subtarget.inMips16Mode()) + return; // no need to load GP. It can be calculated anywhere + + // For O32 ABI, the following instruction sequence is emitted to initialize // the global base register: // -- cgit v1.2.3