From a7a5854f1c3710f4bedf069be4771b81e449f2a3 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Fri, 16 Jun 2006 17:34:12 +0000 Subject: Rename some subtarget features. A CPU now can *have* 64-bit instructions, can in 32-bit mode we can choose to optionally *use* 64-bit registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28824 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPC.td | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'lib/Target/PowerPC/PPC.td') diff --git a/lib/Target/PowerPC/PPC.td b/lib/Target/PowerPC/PPC.td index bc4f3e74e8..6d23657512 100644 --- a/lib/Target/PowerPC/PPC.td +++ b/lib/Target/PowerPC/PPC.td @@ -19,10 +19,10 @@ include "../Target.td" // PowerPC Subtarget features. // -def Feature64Bit : SubtargetFeature<"64bit","Is64Bit", "true", +def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true", "Enable 64-bit instructions">; -def Feature64BitRegs : SubtargetFeature<"64bitregs","Has64BitRegs", "true", - "Enable 64-bit registers [beta]">; +def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true", + "Enable 64-bit registers usage for ppc32 [beta]">; def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true", "Enable Altivec instructions">; def FeatureGPUL : SubtargetFeature<"gpul","IsGigaProcessor", "true", -- cgit v1.2.3