From 80ada583f3b40ffb201e54cd57c42f9518039c9e Mon Sep 17 00:00:00 2001 From: Bill Wendling Date: Fri, 7 Jun 2013 07:55:53 +0000 Subject: Don't cache the instruction and register info from the TargetMachine, because the internals of TargetMachine could change. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183494 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCHazardRecognizers.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'lib/Target/PowerPC/PPCHazardRecognizers.cpp') diff --git a/lib/Target/PowerPC/PPCHazardRecognizers.cpp b/lib/Target/PowerPC/PPCHazardRecognizers.cpp index 4bf1e33964..0df50e17dd 100644 --- a/lib/Target/PowerPC/PPCHazardRecognizers.cpp +++ b/lib/Target/PowerPC/PPCHazardRecognizers.cpp @@ -71,8 +71,8 @@ void PPCScoreboardHazardRecognizer::Reset() { // 3. Handling of the esoteric cases in "Resource-based Instruction Grouping". // -PPCHazardRecognizer970::PPCHazardRecognizer970(const TargetInstrInfo &tii) - : TII(tii) { +PPCHazardRecognizer970::PPCHazardRecognizer970(const TargetMachine &TM) + : TM(TM) { EndDispatchGroup(); } @@ -91,7 +91,7 @@ PPCHazardRecognizer970::GetInstrType(unsigned Opcode, bool &isFirst, bool &isSingle, bool &isCracked, bool &isLoad, bool &isStore) { - const MCInstrDesc &MCID = TII.get(Opcode); + const MCInstrDesc &MCID = TM.getInstrInfo()->get(Opcode); isLoad = MCID.mayLoad(); isStore = MCID.mayStore(); -- cgit v1.2.3