From a5e62019d771fd0b01311cc0136e64b66b299eb1 Mon Sep 17 00:00:00 2001 From: Rafael Espindola Date: Thu, 26 May 2011 19:25:47 +0000 Subject: Fix some dwarf register numbers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132136 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCRegisterInfo.td | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'lib/Target/PowerPC/PPCRegisterInfo.td') diff --git a/lib/Target/PowerPC/PPCRegisterInfo.td b/lib/Target/PowerPC/PPCRegisterInfo.td index 26391657fd..da98ef070a 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.td +++ b/lib/Target/PowerPC/PPCRegisterInfo.td @@ -256,7 +256,7 @@ def CTR : SPR<9, "ctr">, DwarfRegNum<[66]>; def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66]>; // VRsave register -def VRSAVE: SPR<256, "VRsave">, DwarfRegNum<[107]>; +def VRSAVE: SPR<256, "VRsave">, DwarfRegNum<[109]>; // Carry bit. In the architecture this is really bit 0 of the XER register // (which really is SPR register 1); this is the only bit interesting to a -- cgit v1.2.3