From 16803097fbefa313fdadc3adede659bd0e52cec1 Mon Sep 17 00:00:00 2001 From: Hal Finkel Date: Tue, 12 Jun 2012 19:01:24 +0000 Subject: Split out the PPC instruction class IntSimple from IntGeneral. On the POWER7, adds and logical operations can also be handled in the load/store pipelines. We'll call these IntSimple. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158366 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCSchedule440.td | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'lib/Target/PowerPC/PPCSchedule440.td') diff --git a/lib/Target/PowerPC/PPCSchedule440.td b/lib/Target/PowerPC/PPCSchedule440.td index 9921fc8b95..cd0fb70a24 100644 --- a/lib/Target/PowerPC/PPCSchedule440.td +++ b/lib/Target/PowerPC/PPCSchedule440.td @@ -108,6 +108,15 @@ def PPC440Itineraries : ProcessorItineraries< IRACC, IEXE1, IEXE2, IWB, LRACC, JEXE1, JEXE2, JWB, AGEN, CRD, LWB, FEXE1, FEXE2, FEXE3, FEXE4, FEXE5, FEXE6, FWB, LWARX_Hold], [GPR_Bypass, FPR_Bypass], [ + InstrItinData, + InstrStage<1, [PDCD1, PDCD2]>, + InstrStage<1, [DISS1, DISS2]>, + InstrStage<1, [IRACC, LRACC]>, + InstrStage<1, [IEXE1, JEXE1]>, + InstrStage<1, [IEXE2, JEXE2]>, + InstrStage<1, [IWB, JWB]>], + [6, 4, 4], + [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, InstrItinData, InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [DISS1, DISS2]>, -- cgit v1.2.3