From 4d989ac93ce608057fb6b13a4068264ab037ecd5 Mon Sep 17 00:00:00 2001 From: Hal Finkel Date: Sun, 1 Apr 2012 19:22:40 +0000 Subject: Add instruction itinerary for the PPC64 A2 core. This adds a full itinerary for IBM's PPC64 A2 embedded core. These cores form the basis for the CPUs in the new IBM BG/Q supercomputer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153842 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCSubtarget.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'lib/Target/PowerPC/PPCSubtarget.cpp') diff --git a/lib/Target/PowerPC/PPCSubtarget.cpp b/lib/Target/PowerPC/PPCSubtarget.cpp index c89fab3356..fa54a44029 100644 --- a/lib/Target/PowerPC/PPCSubtarget.cpp +++ b/lib/Target/PowerPC/PPCSubtarget.cpp @@ -146,7 +146,7 @@ bool PPCSubtarget::enablePostRAScheduler( CodeGenOpt::Level OptLevel, TargetSubtargetInfo::AntiDepBreakMode& Mode, RegClassVector& CriticalPathRCs) const { - if (DarwinDirective == PPC::DIR_440) + if (DarwinDirective == PPC::DIR_440 || DarwinDirective == PPC::DIR_A2) return false; Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL; -- cgit v1.2.3