From 9a256300f8f61937f5f7a148b9cb09936d103a97 Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Mon, 15 Apr 2013 17:51:35 +0000 Subject: R600/SI: Emit config values in register value pairs. Instead of emitting config values in a predefined order, the code emitter will now emit a 32-bit register index followed by the 32-bit config value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179546 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/R600/SIDefines.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 lib/Target/R600/SIDefines.h (limited to 'lib/Target/R600/SIDefines.h') diff --git a/lib/Target/R600/SIDefines.h b/lib/Target/R600/SIDefines.h new file mode 100644 index 0000000000..716b093fc6 --- /dev/null +++ b/lib/Target/R600/SIDefines.h @@ -0,0 +1,22 @@ +//===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +/// \file +//===----------------------------------------------------------------------===// + +#ifndef SIDEFINES_H_ +#define SIDEFINES_H_ + +#define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028 +#define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128 +#define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228 +#define R_00B848_COMPUTE_PGM_RSRC1 0x00B848 +#define S_00B028_VGPRS(x) (((x) & 0x3F) << 0) +#define S_00B028_SGPRS(x) (((x) & 0x0F) << 6) +#define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC + +#endif // SIDEFINES_H_ -- cgit v1.2.3