From 836c5133c66edecedeaa79448964b4c103f99271 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Mon, 18 Nov 2013 20:09:21 +0000 Subject: R600/SI: Fix extra defs of VCC / SCC. When replacing scalar operations with vector, the wrong implicit output register was used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195033 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/R600/SIInstrInfo.cpp | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) (limited to 'lib/Target/R600') diff --git a/lib/Target/R600/SIInstrInfo.cpp b/lib/Target/R600/SIInstrInfo.cpp index 11710b42e6..9d8dff19c6 100644 --- a/lib/Target/R600/SIInstrInfo.cpp +++ b/lib/Target/R600/SIInstrInfo.cpp @@ -466,6 +466,8 @@ void SIInstrInfo::legalizeOperands(MachineInstr *MI) const { if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg()))) continue; // VGPRs are legal + assert(MO.getReg() != AMDGPU::SCC && "SCC operand to VOP3 instruction"); + if (SGPRReg == AMDGPU::NoRegister || SGPRReg == MO.getReg()) { SGPRReg = MO.getReg(); // We can use one SGPR in each VOP3 instruction. @@ -543,18 +545,27 @@ void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const { const MCInstrDesc &NewDesc = get(NewOpcode); Inst->setDesc(NewDesc); + // Remove any references to SCC. Vector instructions can't read from it, and + // We're just about to add the implicit use / defs of VCC, and we don't want + // both. + for (unsigned i = Inst->getNumOperands() - 1; i > 0; --i) { + MachineOperand &Op = Inst->getOperand(i); + if (Op.isReg() && Op.getReg() == AMDGPU::SCC) + Inst->RemoveOperand(i); + } + // Add the implict and explicit register definitions. if (NewDesc.ImplicitUses) { for (unsigned i = 0; NewDesc.ImplicitUses[i]; ++i) { - Inst->addOperand(MachineOperand::CreateReg(NewDesc.ImplicitUses[i], - false, true)); + unsigned Reg = NewDesc.ImplicitUses[i]; + Inst->addOperand(MachineOperand::CreateReg(Reg, false, true)); } } if (NewDesc.ImplicitDefs) { for (unsigned i = 0; NewDesc.ImplicitDefs[i]; ++i) { - Inst->addOperand(MachineOperand::CreateReg(NewDesc.ImplicitDefs[i], - true, true)); + unsigned Reg = NewDesc.ImplicitDefs[i]; + Inst->addOperand(MachineOperand::CreateReg(Reg, true, true)); } } -- cgit v1.2.3