From 1d6d49fbb104781cc3e9da9dcc3e36b6cbcd38b6 Mon Sep 17 00:00:00 2001 From: Roman Divacky Date: Thu, 31 Oct 2013 19:22:33 +0000 Subject: SparcV9 doesnt have rem instruction either. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193789 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Sparc/SparcISelLowering.cpp | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'lib/Target/Sparc/SparcISelLowering.cpp') diff --git a/lib/Target/Sparc/SparcISelLowering.cpp b/lib/Target/Sparc/SparcISelLowering.cpp index c2e16fc219..d0156fa340 100644 --- a/lib/Target/Sparc/SparcISelLowering.cpp +++ b/lib/Target/Sparc/SparcISelLowering.cpp @@ -1341,6 +1341,14 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) setOperationAction(ISD::SREM, MVT::i32, Expand); setOperationAction(ISD::SDIVREM, MVT::i32, Expand); setOperationAction(ISD::UDIVREM, MVT::i32, Expand); + + // ... nor does SparcV9. + if (Subtarget->is64Bit()) { + setOperationAction(ISD::UREM, MVT::i64, Expand); + setOperationAction(ISD::SREM, MVT::i64, Expand); + setOperationAction(ISD::SDIVREM, MVT::i64, Expand); + setOperationAction(ISD::UDIVREM, MVT::i64, Expand); + } // Custom expand fp<->sint setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); -- cgit v1.2.3