From 66f0f640820b61cf9db814b6d187bae9faf7279c Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Fri, 5 Oct 2007 01:32:41 +0000 Subject: - Added a few target hooks to generate load / store instructions from / to any address (not just from / to frameindexes). - Added target hooks to unfold load / store instructions / SDNodes into separate load, data processing, store instructions / SDNodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42621 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Sparc/SparcRegisterInfo.cpp | 55 ++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) (limited to 'lib/Target/Sparc/SparcRegisterInfo.cpp') diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp index d3ea07b121..7129f43712 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.cpp +++ b/lib/Target/Sparc/SparcRegisterInfo.cpp @@ -48,6 +48,34 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, assert(0 && "Can't store this register to stack slot"); } +void SparcRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, + SmallVector Addr, + const TargetRegisterClass *RC, + SmallVector &NewMIs) const { + unsigned Opc = 0; + if (RC == SP::IntRegsRegisterClass) + Opc = SP::STri; + else if (RC == SP::FPRegsRegisterClass) + Opc = SP::STFri; + else if (RC == SP::DFPRegsRegisterClass) + Opc = SP::STDFri; + else + assert(0 && "Can't load this register"); + MachineInstrBuilder MIB = BuildMI(TII.get(Opc)); + for (unsigned i = 0, e = Addr.size(); i != e; ++i) { + MachineOperand &MO = Addr[i]; + if (MO.isRegister()) + MIB.addReg(MO.getReg()); + else if (MO.isImmediate()) + MIB.addImm(MO.getImmedValue()); + else + MIB.addFrameIndex(MO.getFrameIndex()); + } + MIB.addReg(SrcReg, false, false, true); + NewMIs.push_back(MIB); + return; +} + void SparcRegisterInfo:: loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, @@ -62,6 +90,33 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, assert(0 && "Can't load this register from stack slot"); } +void SparcRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, + SmallVector Addr, + const TargetRegisterClass *RC, + SmallVector &NewMIs) const { + unsigned Opc = 0; + if (RC == SP::IntRegsRegisterClass) + Opc = SP::LDri; + else if (RC == SP::FPRegsRegisterClass) + Opc = SP::LDFri; + else if (RC == SP::DFPRegsRegisterClass) + Opc = SP::LDDFri; + else + assert(0 && "Can't load this register"); + MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg); + for (unsigned i = 0, e = Addr.size(); i != e; ++i) { + MachineOperand &MO = Addr[i]; + if (MO.isRegister()) + MIB.addReg(MO.getReg()); + else if (MO.isImmediate()) + MIB.addImm(MO.getImmedValue()); + else + MIB.addFrameIndex(MO.getFrameIndex()); + } + NewMIs.push_back(MIB); + return; +} + void SparcRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, unsigned SrcReg, -- cgit v1.2.3