From 30a132f7676ec5465a2245cb94e7bd9214ea8eb7 Mon Sep 17 00:00:00 2001
From: Richard Sandiford <rsandifo@linux.vnet.ibm.com>
Date: Thu, 18 Jul 2013 10:06:15 +0000
Subject: [SystemZ] Use RXSBG

Extend the previous R.SBG patches to handle XORs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186570 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/SystemZ/SystemZISelDAGToDAG.cpp | 27 ++++++++++++++++-----------
 1 file changed, 16 insertions(+), 11 deletions(-)

(limited to 'lib/Target/SystemZ/SystemZISelDAGToDAG.cpp')

diff --git a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
index aea08083c5..67e9d217ee 100644
--- a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
+++ b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
@@ -241,9 +241,9 @@ class SystemZDAGToDAGISel : public SelectionDAGISel {
   // Return the selected node on success, otherwise return null.
   SDNode *tryRISBGZero(SDNode *N);
 
-  // Try to use RISBG or ROSBG to implement OR node N.  Return the selected
-  // node on success, otherwise return null.
-  SDNode *tryRISBGOrROSBG(SDNode *N);
+  // Try to use RISBG or Opcode to implement OR or XOR node N.
+  // Return the selected node on success, otherwise return null.
+  SDNode *tryRxSBG(SDNode *N, unsigned Opcode);
 
   // If Op0 is null, then Node is a constant that can be loaded using:
   //
@@ -799,8 +799,8 @@ SDNode *SystemZDAGToDAGISel::tryRISBGZero(SDNode *N) {
   return convertTo(SDLoc(N), VT, SDValue(N, 0)).getNode();
 }
 
-SDNode *SystemZDAGToDAGISel::tryRISBGOrROSBG(SDNode *N) {
-  // Try treating each operand of N as the second operand of RISBG or ROSBG
+SDNode *SystemZDAGToDAGISel::tryRxSBG(SDNode *N, unsigned Opcode) {
+  // Try treating each operand of N as the second operand of the RxSBG
   // and see which goes deepest.
   RxSBGOperands RxSBG[] = { N->getOperand(0), N->getOperand(1) };
   unsigned Count[] = { 0, 0 };
@@ -817,15 +817,14 @@ SDNode *SystemZDAGToDAGISel::tryRISBGOrROSBG(SDNode *N) {
   SDValue Op0 = N->getOperand(I ^ 1);
 
   // Prefer IC for character insertions from memory.
-  if ((RxSBG[I].Mask & 0xff) == 0)
+  if (Opcode == SystemZ::ROSBG && (RxSBG[I].Mask & 0xff) == 0)
     if (LoadSDNode *Load = dyn_cast<LoadSDNode>(Op0.getNode()))
       if (Load->getMemoryVT() == MVT::i8)
         return 0;
 
   // See whether we can avoid an AND in the first operand by converting
   // ROSBG to RISBG.
-  unsigned Opcode = SystemZ::ROSBG;
-  if (detectOrAndInsertion(Op0, RxSBG[I].Mask))
+  if (Opcode == SystemZ::ROSBG && detectOrAndInsertion(Op0, RxSBG[I].Mask))
     Opcode = SystemZ::RISBG;
            
   EVT VT = N->getValueType(0);
@@ -913,9 +912,14 @@ SDNode *SystemZDAGToDAGISel::Select(SDNode *Node) {
   switch (Opcode) {
   case ISD::OR:
     if (Node->getOperand(1).getOpcode() != ISD::Constant)
-      ResNode = tryRISBGOrROSBG(Node);
-    // Fall through.
+      ResNode = tryRxSBG(Node, SystemZ::ROSBG);
+    goto or_xor;
+
   case ISD::XOR:
+    if (Node->getOperand(1).getOpcode() != ISD::Constant)
+      ResNode = tryRxSBG(Node, SystemZ::RXSBG);
+    // Fall through.
+  or_xor:
     // If this is a 64-bit operation in which both 32-bit halves are nonzero,
     // split the operation into two.
     if (!ResNode && Node->getValueType(0) == MVT::i64)
@@ -931,7 +935,8 @@ SDNode *SystemZDAGToDAGISel::Select(SDNode *Node) {
   case ISD::ROTL:
   case ISD::SHL:
   case ISD::SRL:
-    ResNode = tryRISBGZero(Node);
+    if (!ResNode)
+      ResNode = tryRISBGZero(Node);
     break;
 
   case ISD::Constant:
-- 
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