From 720e3b00b869950bdc09ad065d92174772903da0 Mon Sep 17 00:00:00 2001
From: Anton Korobeynikov <asl@math.spbu.ru>
Date: Thu, 16 Jul 2009 14:09:35 +0000
Subject: Add support for 12 bit displacements

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75988 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/SystemZ/SystemZOperands.td | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

(limited to 'lib/Target/SystemZ/SystemZOperands.td')

diff --git a/lib/Target/SystemZ/SystemZOperands.td b/lib/Target/SystemZ/SystemZOperands.td
index 446e426abf..7ac6cc28c1 100644
--- a/lib/Target/SystemZ/SystemZOperands.td
+++ b/lib/Target/SystemZ/SystemZOperands.td
@@ -214,10 +214,14 @@ def i64i32imm : Operand<i64>;
 // Branch targets have OtherVT type.
 def brtarget : Operand<OtherVT>;
 
-// Unigned i12
+// Unsigned i12
 def u12imm : Operand<i32> {
-  let PrintMethod = "printU16ImmOperand";
+  let PrintMethod = "printU12ImmOperand";
 }
+def u12imm64 : Operand<i64> {
+  let PrintMethod = "printU12ImmOperand";
+}
+
 // Signed i16
 def s16imm : Operand<i32> {
   let PrintMethod = "printS16ImmOperand";
@@ -262,8 +266,13 @@ def riaddr : Operand<i64>,
 //===----------------------------------------------------------------------===//
 
 // rriaddr := reg + reg + imm
+def rriaddr12 : Operand<i64>,
+                ComplexPattern<i64, 3, "SelectAddrRRI12", [], []> {
+  let PrintMethod = "printRRIAddrOperand";
+  let MIOperandInfo = (ops ADDR64:$base, u12imm64:$disp, ADDR64:$index);
+}
 def rriaddr : Operand<i64>,
-              ComplexPattern<i64, 3, "SelectAddrRRI", [], []> {
+              ComplexPattern<i64, 3, "SelectAddrRRI20", [], []> {
   let PrintMethod = "printRRIAddrOperand";
   let MIOperandInfo = (ops ADDR64:$base, s20imm64:$disp, ADDR64:$index);
 }
-- 
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