From 514756983e9ba3684a89ed583bf5a98ffb20c203 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Mon, 30 Sep 2013 08:48:38 +0000 Subject: [SystemZ] Rename 32-bit GPR registers I'm about to add support for high-word operations, so it seemed better for the low-word registers to have names like R0L rather than R0W. No behavioral change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191655 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp | 8 ++++---- lib/Target/SystemZ/SystemZCallingConv.td | 4 ++-- lib/Target/SystemZ/SystemZISelLowering.cpp | 10 +++++----- lib/Target/SystemZ/SystemZInstrInfo.td | 6 +++--- lib/Target/SystemZ/SystemZRegisterInfo.cpp | 4 ++-- lib/Target/SystemZ/SystemZRegisterInfo.td | 8 ++++---- 6 files changed, 20 insertions(+), 20 deletions(-) (limited to 'lib/Target/SystemZ') diff --git a/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp b/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp index cb97bcaaa1..f17a621367 100644 --- a/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp +++ b/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp @@ -28,10 +28,10 @@ using namespace llvm; const unsigned SystemZMC::GR32Regs[16] = { - SystemZ::R0W, SystemZ::R1W, SystemZ::R2W, SystemZ::R3W, - SystemZ::R4W, SystemZ::R5W, SystemZ::R6W, SystemZ::R7W, - SystemZ::R8W, SystemZ::R9W, SystemZ::R10W, SystemZ::R11W, - SystemZ::R12W, SystemZ::R13W, SystemZ::R14W, SystemZ::R15W + SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, + SystemZ::R4L, SystemZ::R5L, SystemZ::R6L, SystemZ::R7L, + SystemZ::R8L, SystemZ::R9L, SystemZ::R10L, SystemZ::R11L, + SystemZ::R12L, SystemZ::R13L, SystemZ::R14L, SystemZ::R15L }; const unsigned SystemZMC::GR64Regs[16] = { diff --git a/lib/Target/SystemZ/SystemZCallingConv.td b/lib/Target/SystemZ/SystemZCallingConv.td index c2d727fe4d..c4f641e7bd 100644 --- a/lib/Target/SystemZ/SystemZCallingConv.td +++ b/lib/Target/SystemZ/SystemZCallingConv.td @@ -23,7 +23,7 @@ def RetCC_SystemZ : CallingConv<[ // call-clobbered argument registers available for code that doesn't // care about the ABI. (R6 is an argument register too, but is // call-saved and therefore not suitable for return values.) - CCIfType<[i32], CCAssignToReg<[R2W, R3W, R4W, R5W]>>, + CCIfType<[i32], CCAssignToReg<[R2L, R3L, R4L, R5L]>>, CCIfType<[i64], CCAssignToReg<[R2D, R3D, R4D, R5D]>>, // ABI-complaint code returns float and double in F0. Make the @@ -53,7 +53,7 @@ def CC_SystemZ : CallingConv<[ // The first 5 integer arguments are passed in R2-R6. Note that R6 // is call-saved. - CCIfType<[i32], CCAssignToReg<[R2W, R3W, R4W, R5W, R6W]>>, + CCIfType<[i32], CCAssignToReg<[R2L, R3L, R4L, R5L, R6L]>>, CCIfType<[i64], CCAssignToReg<[R2D, R3D, R4D, R5D, R6D]>>, // The first 4 float and double arguments are passed in even registers F0-F6. diff --git a/lib/Target/SystemZ/SystemZISelLowering.cpp b/lib/Target/SystemZ/SystemZISelLowering.cpp index ff4e7cab42..5d8b76ba71 100644 --- a/lib/Target/SystemZ/SystemZISelLowering.cpp +++ b/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -733,7 +733,7 @@ static bool canUseSiblingCall(CCState ArgCCInfo, if (!VA.isRegLoc()) return false; unsigned Reg = VA.getLocReg(); - if (Reg == SystemZ::R6W || Reg == SystemZ::R6D) + if (Reg == SystemZ::R6L || Reg == SystemZ::R6D) return false; } return true; @@ -2834,12 +2834,12 @@ SystemZTargetLowering::emitStringWrapper(MachineInstr *MI, // LoopMBB: // %This1Reg = phi [ %Start1Reg, StartMBB ], [ %End1Reg, LoopMBB ] // %This2Reg = phi [ %Start2Reg, StartMBB ], [ %End2Reg, LoopMBB ] - // R0W = %CharReg - // %End1Reg, %End2Reg = CLST %This1Reg, %This2Reg -- uses R0W + // R0L = %CharReg + // %End1Reg, %End2Reg = CLST %This1Reg, %This2Reg -- uses R0L // JO LoopMBB // # fall through to DoneMMB // - // The load of R0W can be hoisted by post-RA LICM. + // The load of R0L can be hoisted by post-RA LICM. MBB = LoopMBB; BuildMI(MBB, DL, TII->get(SystemZ::PHI), This1Reg) @@ -2848,7 +2848,7 @@ SystemZTargetLowering::emitStringWrapper(MachineInstr *MI, BuildMI(MBB, DL, TII->get(SystemZ::PHI), This2Reg) .addReg(Start2Reg).addMBB(StartMBB) .addReg(End2Reg).addMBB(LoopMBB); - BuildMI(MBB, DL, TII->get(TargetOpcode::COPY), SystemZ::R0W).addReg(CharReg); + BuildMI(MBB, DL, TII->get(TargetOpcode::COPY), SystemZ::R0L).addReg(CharReg); BuildMI(MBB, DL, TII->get(Opcode)) .addReg(End1Reg, RegState::Define).addReg(End2Reg, RegState::Define) .addReg(This1Reg).addReg(This2Reg); diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td index d2aa2760b5..16b9cfdaa7 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.td +++ b/lib/Target/SystemZ/SystemZInstrInfo.td @@ -361,7 +361,7 @@ let mayLoad = 1, mayStore = 1 in defm MVC : MemorySS<"mvc", 0xD2, z_mvc, z_mvc_loop>; // String moves. -let mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0W] in +let mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0L] in defm MVST : StringRRE<"mvst", 0xB255, z_stpcpy>; //===----------------------------------------------------------------------===// @@ -1023,7 +1023,7 @@ let mayLoad = 1, Defs = [CC] in defm CLC : MemorySS<"clc", 0xD5, z_clc, z_clc_loop>; // String comparison. -let mayLoad = 1, Defs = [CC], Uses = [R0W] in +let mayLoad = 1, Defs = [CC], Uses = [R0L] in defm CLST : StringRRE<"clst", 0xB25D, z_strcmp>; // Test under mask. @@ -1198,7 +1198,7 @@ let usesCustomInserter = 1 in { } // Search a block of memory for a character. -let mayLoad = 1, Defs = [CC], Uses = [R0W] in +let mayLoad = 1, Defs = [CC], Uses = [R0L] in defm SRST : StringRRE<"srst", 0xb25e, z_search_string>; //===----------------------------------------------------------------------===// diff --git a/lib/Target/SystemZ/SystemZRegisterInfo.cpp b/lib/Target/SystemZ/SystemZRegisterInfo.cpp index 8ce6d6ab44..841f0ae026 100644 --- a/lib/Target/SystemZ/SystemZRegisterInfo.cpp +++ b/lib/Target/SystemZ/SystemZRegisterInfo.cpp @@ -42,13 +42,13 @@ SystemZRegisterInfo::getReservedRegs(const MachineFunction &MF) const { if (TFI->hasFP(MF)) { // R11D is the frame pointer. Reserve all aliases. Reserved.set(SystemZ::R11D); - Reserved.set(SystemZ::R11W); + Reserved.set(SystemZ::R11L); Reserved.set(SystemZ::R10Q); } // R15D is the stack pointer. Reserve all aliases. Reserved.set(SystemZ::R15D); - Reserved.set(SystemZ::R15W); + Reserved.set(SystemZ::R15L); Reserved.set(SystemZ::R14Q); return Reserved; } diff --git a/lib/Target/SystemZ/SystemZRegisterInfo.td b/lib/Target/SystemZ/SystemZRegisterInfo.td index ffffe721cb..0821d02060 100644 --- a/lib/Target/SystemZ/SystemZRegisterInfo.td +++ b/lib/Target/SystemZ/SystemZRegisterInfo.td @@ -70,8 +70,8 @@ class GPR128 num, string n, GPR64 high, GPR64 low> // General-purpose registers foreach I = 0-15 in { - def R#I#W : GPR32; - def R#I#D : GPR64("R"#I#"W")>, DwarfRegNum<[I]>; + def R#I#L : GPR32; + def R#I#D : GPR64("R"#I#"L")>, DwarfRegNum<[I]>; } foreach I = [0, 2, 4, 6, 8, 10, 12, 14] in { @@ -81,8 +81,8 @@ foreach I = [0, 2, 4, 6, 8, 10, 12, 14] in { /// Allocate the callee-saved R6-R13 backwards. That way they can be saved /// together with R14 and R15 in one prolog instruction. -defm GR32 : SystemZRegClass<"GR32", i32, 32, (add (sequence "R%uW", 0, 5), - (sequence "R%uW", 15, 6))>; +defm GR32 : SystemZRegClass<"GR32", i32, 32, (add (sequence "R%uL", 0, 5), + (sequence "R%uL", 15, 6))>; defm GR64 : SystemZRegClass<"GR64", i64, 64, (add (sequence "R%uD", 0, 5), (sequence "R%uD", 15, 6))>; -- cgit v1.2.3