From f654554ee0693770308e187df9d411c8a51bebde Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper@gmail.com>
Date: Fri, 20 Jul 2012 07:03:46 +0000
Subject: Don't use implicit register operands to calculate L-bit for AVX
 instructions. Needed because super reg defs and kills are added as implicit
 operands on 128-bit instructions. Fixes PR13349. Patch by Jose Fonseca.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160543 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/X86/X86CodeEmitter.cpp | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'lib/Target/X86/X86CodeEmitter.cpp')

diff --git a/lib/Target/X86/X86CodeEmitter.cpp b/lib/Target/X86/X86CodeEmitter.cpp
index 977cc50c13..d7050495f8 100644
--- a/lib/Target/X86/X86CodeEmitter.cpp
+++ b/lib/Target/X86/X86CodeEmitter.cpp
@@ -927,6 +927,8 @@ void Emitter<CodeEmitter>::emitVEXOpcodePrefix(uint64_t TSFlags,
   for (unsigned i = 0; i != MI.getNumOperands(); ++i) {
     if (!MI.getOperand(i).isReg())
       continue;
+    if (MI.getOperand(i).isImplicit())
+      continue;
     unsigned SrcReg = MI.getOperand(i).getReg();
     if (SrcReg >= X86::YMM0 && SrcReg <= X86::YMM15)
       VEX_L = 1;
-- 
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