From 0e6a052331f674dd70e28af41f654a7874405eab Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Mon, 18 Jul 2011 20:57:22 +0000 Subject: Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo down to MCRegisterInfo. Also initialize the mapping at construction time. This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step towards fixing the layering violation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135424 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp') diff --git a/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp b/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp index 939d97c9d8..a29f160d41 100644 --- a/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp +++ b/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp @@ -39,6 +39,16 @@ extern "C" void LLVMInitializeXCoreMCInstrInfo() { TargetRegistry::RegisterMCInstrInfo(TheXCoreTarget, createXCoreMCInstrInfo); } +static MCRegisterInfo *createXCoreMCRegisterInfo(StringRef TT) { + MCRegisterInfo *X = new MCRegisterInfo(); + InitXCoreMCRegisterInfo(X, XCore::LR); + return X; +} + +extern "C" void LLVMInitializeXCoreMCRegisterInfo() { + TargetRegistry::RegisterMCRegInfo(TheXCoreTarget, createXCoreMCRegisterInfo); +} + static MCSubtargetInfo *createXCoreMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) { MCSubtargetInfo *X = new MCSubtargetInfo(); -- cgit v1.2.3