From a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576d Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Fri, 24 Jun 2011 01:44:41 +0000 Subject: Starting to refactor Target to separate out code that's needed to fully describe target machine from those that are only needed by codegen. The goal is to sink the essential target description into MC layer so we can start building MC based tools without needing to link in the entire codegen. First step is to refactor TargetRegisterInfo. This patch added a base class MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to separate register description from the rest of the stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133782 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/XCore/Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'lib/Target/XCore/Makefile') diff --git a/lib/Target/XCore/Makefile b/lib/Target/XCore/Makefile index 6c1ef88603..f67ef517a1 100644 --- a/lib/Target/XCore/Makefile +++ b/lib/Target/XCore/Makefile @@ -13,7 +13,8 @@ TARGET = XCore # Make sure that tblgen is run, first thing. BUILT_SOURCES = XCoreGenRegisterInfo.h.inc XCoreGenRegisterNames.inc \ - XCoreGenRegisterInfo.inc XCoreGenInstrNames.inc \ + XCoreGenRegisterInfo.inc XCoreGenRegisterDesc.inc \ + XCoreGenInstrNames.inc \ XCoreGenInstrInfo.inc XCoreGenAsmWriter.inc \ XCoreGenDAGISel.inc XCoreGenCallingConv.inc \ XCoreGenSubtarget.inc -- cgit v1.2.3