From 2973b57093b017f2e3b5f5edd0be9d4ea180f0e9 Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Wed, 6 Jan 2010 16:48:02 +0000 Subject: 80 column and whitespace cleanup git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92837 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/AggressiveAntiDepBreaker.cpp | 159 ++++++++++++++++--------------- lib/CodeGen/AggressiveAntiDepBreaker.h | 28 +++--- lib/CodeGen/CriticalAntiDepBreaker.cpp | 11 ++- lib/CodeGen/CriticalAntiDepBreaker.h | 5 +- 4 files changed, 108 insertions(+), 95 deletions(-) (limited to 'lib') diff --git a/lib/CodeGen/AggressiveAntiDepBreaker.cpp b/lib/CodeGen/AggressiveAntiDepBreaker.cpp index 761fbc6870..ca1f4a3e01 100644 --- a/lib/CodeGen/AggressiveAntiDepBreaker.cpp +++ b/lib/CodeGen/AggressiveAntiDepBreaker.cpp @@ -1,4 +1,4 @@ -//===----- AggressiveAntiDepBreaker.cpp - Anti-dep breaker -------- ---------===// +//===----- AggressiveAntiDepBreaker.cpp - Anti-dep breaker ----------------===// // // The LLVM Compiler Infrastructure // @@ -77,18 +77,18 @@ unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2) { assert(GroupNodes[0] == 0 && "GroupNode 0 not parent!"); assert(GroupNodeIndices[0] == 0 && "Reg 0 not in Group 0!"); - + // find group for each register unsigned Group1 = GetGroup(Reg1); unsigned Group2 = GetGroup(Reg2); - + // if either group is 0, then that must become the parent unsigned Parent = (Group1 == 0) ? Group1 : Group2; unsigned Other = (Parent == Group1) ? Group2 : Group1; GroupNodes.at(Other) = Parent; return Parent; } - + unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg) { // Create a new GroupNode for Reg. Reg's existing GroupNode must @@ -111,7 +111,7 @@ bool AggressiveAntiDepState::IsLive(unsigned Reg) AggressiveAntiDepBreaker:: AggressiveAntiDepBreaker(MachineFunction& MFi, - TargetSubtarget::RegClassVector& CriticalPathRCs) : + TargetSubtarget::RegClassVector& CriticalPathRCs) : AntiDepBreaker(), MF(MFi), MRI(MF.getRegInfo()), TRI(MF.getTarget().getRegisterInfo()), @@ -126,9 +126,9 @@ AggressiveAntiDepBreaker(MachineFunction& MFi, else CriticalPathSet |= CPSet; } - + DEBUG(dbgs() << "AntiDep Critical-Path Registers:"); - DEBUG(for (int r = CriticalPathSet.find_first(); r != -1; + DEBUG(for (int r = CriticalPathSet.find_first(); r != -1; r = CriticalPathSet.find_next(r)) dbgs() << " " << TRI->getName(r)); DEBUG(dbgs() << '\n'); @@ -232,10 +232,11 @@ void AggressiveAntiDepBreaker::Observe(MachineInstr *MI, unsigned Count, // schedule region). if (State->IsLive(Reg)) { DEBUG(if (State->GetGroup(Reg) != 0) - dbgs() << " " << TRI->getName(Reg) << "=g" << + dbgs() << " " << TRI->getName(Reg) << "=g" << State->GetGroup(Reg) << "->g0(region live-out)"); State->UnionGroups(Reg, 0); - } else if ((DefIndices[Reg] < InsertPosIndex) && (DefIndices[Reg] >= Count)) { + } else if ((DefIndices[Reg] < InsertPosIndex) + && (DefIndices[Reg] >= Count)) { DefIndices[Reg] = Count; } } @@ -266,7 +267,7 @@ void AggressiveAntiDepBreaker::GetPassthruRegs(MachineInstr *MI, for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &MO = MI->getOperand(i); if (!MO.isReg()) continue; - if ((MO.isDef() && MI->isRegTiedToUseOperand(i)) || + if ((MO.isDef() && MI->isRegTiedToUseOperand(i)) || IsImplicitDefUse(MI, MO)) { const unsigned Reg = MO.getReg(); PassthruRegs.insert(Reg); @@ -320,11 +321,12 @@ static SUnit *CriticalPathStep(SUnit *SU) { } void AggressiveAntiDepBreaker::HandleLastUse(unsigned Reg, unsigned KillIdx, - const char *tag, const char *header, + const char *tag, + const char *header, const char *footer) { unsigned *KillIndices = State->GetKillIndices(); unsigned *DefIndices = State->GetDefIndices(); - std::multimap& + std::multimap& RegRefs = State->GetRegRefs(); if (!State->IsLive(Reg)) { @@ -355,10 +357,12 @@ void AggressiveAntiDepBreaker::HandleLastUse(unsigned Reg, unsigned KillIdx, DEBUG(if ((header == NULL) && (footer != NULL)) dbgs() << footer); } -void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI, unsigned Count, - std::set& PassthruRegs) { +void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI, + unsigned Count, + std::set& PassthruRegs) +{ unsigned *DefIndices = State->GetDefIndices(); - std::multimap& + std::multimap& RegRefs = State->GetRegRefs(); // Handle dead defs by simulating a last-use of the register just @@ -371,7 +375,7 @@ void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI, unsigned Cou if (!MO.isReg() || !MO.isDef()) continue; unsigned Reg = MO.getReg(); if (Reg == 0) continue; - + HandleLastUse(Reg, Count + 1, "", "\tDead Def: ", "\n"); } @@ -382,7 +386,7 @@ void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI, unsigned Cou unsigned Reg = MO.getReg(); if (Reg == 0) continue; - DEBUG(dbgs() << " " << TRI->getName(Reg) << "=g" << State->GetGroup(Reg)); + DEBUG(dbgs() << " " << TRI->getName(Reg) << "=g" << State->GetGroup(Reg)); // If MI's defs have a special allocation requirement, don't allow // any def registers to be changed. Also assume all registers @@ -398,11 +402,11 @@ void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI, unsigned Cou unsigned AliasReg = *Alias; if (State->IsLive(AliasReg)) { State->UnionGroups(Reg, AliasReg); - DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << "(via " << + DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << "(via " << TRI->getName(AliasReg) << ")"); } } - + // Note register reference... const TargetRegisterClass *RC = NULL; if (i < MI->getDesc().getNumOperands()) @@ -438,7 +442,7 @@ void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI, unsigned Cou void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr *MI, unsigned Count) { DEBUG(dbgs() << "\tUse Groups:"); - std::multimap& + std::multimap& RegRefs = State->GetRegRefs(); // Scan the register uses for this instruction and update @@ -448,9 +452,9 @@ void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr *MI, if (!MO.isReg() || !MO.isUse()) continue; unsigned Reg = MO.getReg(); if (Reg == 0) continue; - - DEBUG(dbgs() << " " << TRI->getName(Reg) << "=g" << - State->GetGroup(Reg)); + + DEBUG(dbgs() << " " << TRI->getName(Reg) << "=g" << + State->GetGroup(Reg)); // It wasn't previously live but now it is, this is a kill. Forget // the previous live-range information and start a new live-range @@ -472,7 +476,7 @@ void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr *MI, AggressiveAntiDepState::RegisterReference RR = { &MO, RC }; RegRefs.insert(std::make_pair(Reg, RR)); } - + DEBUG(dbgs() << '\n'); // Form a group of all defs and uses of a KILL instruction to ensure @@ -486,7 +490,7 @@ void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr *MI, if (!MO.isReg()) continue; unsigned Reg = MO.getReg(); if (Reg == 0) continue; - + if (FirstReg != 0) { DEBUG(dbgs() << "=" << TRI->getName(Reg)); State->UnionGroups(FirstReg, Reg); @@ -495,7 +499,7 @@ void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr *MI, FirstReg = Reg; } } - + DEBUG(dbgs() << "->g" << State->GetGroup(FirstReg) << '\n'); } } @@ -507,13 +511,14 @@ BitVector AggressiveAntiDepBreaker::GetRenameRegisters(unsigned Reg) { // Check all references that need rewriting for Reg. For each, use // the corresponding register class to narrow the set of registers // that are appropriate for renaming. - std::pair::iterator, std::multimap::iterator> Range = State->GetRegRefs().equal_range(Reg); - for (std::multimap::iterator - Q = Range.first, QE = Range.second; Q != QE; ++Q) { + for (std::multimap::iterator Q = Range.first, + QE = Range.second; Q != QE; ++Q) { const TargetRegisterClass *RC = Q->second.RC; if (RC == NULL) continue; @@ -527,9 +532,9 @@ BitVector AggressiveAntiDepBreaker::GetRenameRegisters(unsigned Reg) { DEBUG(dbgs() << " " << RC->getName()); } - + return BV; -} +} bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters( unsigned AntiDepGroupIndex, @@ -537,7 +542,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters( std::map &RenameMap) { unsigned *KillIndices = State->GetKillIndices(); unsigned *DefIndices = State->GetDefIndices(); - std::multimap& + std::multimap& RegRefs = State->GetRegRefs(); // Collect all referenced registers in the same group as @@ -552,7 +557,8 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters( // Find the "superest" register in the group. At the same time, // collect the BitVector of registers that can be used to rename // each register. - DEBUG(dbgs() << "\tRename Candidates for Group g" << AntiDepGroupIndex << ":\n"); + DEBUG(dbgs() << "\tRename Candidates for Group g" << AntiDepGroupIndex + << ":\n"); std::map RenameRegisterMap; unsigned SuperReg = 0; for (unsigned i = 0, e = Regs.size(); i != e; ++i) { @@ -563,7 +569,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters( // If Reg has any references, then collect possible rename regs if (RegRefs.count(Reg) > 0) { DEBUG(dbgs() << "\t\t" << TRI->getName(Reg) << ":"); - + BitVector BV = GetRenameRegisters(Reg); RenameRegisterMap.insert(std::pair(Reg, BV)); @@ -590,7 +596,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters( static int renamecnt = 0; if (renamecnt++ % DebugDiv != DebugMod) return false; - + dbgs() << "*** Performing rename " << TRI->getName(SuperReg) << " for debug ***\n"; } @@ -600,9 +606,9 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters( // order. If that register is available, and the corresponding // registers are available for the other group subregisters, then we // can use those registers to rename. - const TargetRegisterClass *SuperRC = + const TargetRegisterClass *SuperRC = TRI->getPhysicalRegisterRegClass(SuperReg, MVT::Other); - + const TargetRegisterClass::iterator RB = SuperRC->allocation_order_begin(MF); const TargetRegisterClass::iterator RE = SuperRC->allocation_order_end(MF); if (RB == RE) { @@ -624,7 +630,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters( const unsigned NewSuperReg = *R; // Don't replace a register with itself. if (NewSuperReg == SuperReg) continue; - + DEBUG(dbgs() << " [" << TRI->getName(NewSuperReg) << ':'); RenameMap.clear(); @@ -643,7 +649,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters( } DEBUG(dbgs() << " " << TRI->getName(NewReg)); - + // Check if Reg can be renamed to NewReg. BitVector BV = RenameRegisterMap[Reg]; if (!BV.test(NewReg)) { @@ -663,7 +669,8 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters( for (const unsigned *Alias = TRI->getAliasSet(NewReg); *Alias; ++Alias) { unsigned AliasReg = *Alias; - if (State->IsLive(AliasReg) || (KillIndices[Reg] > DefIndices[AliasReg])) { + if (State->IsLive(AliasReg) || + (KillIndices[Reg] > DefIndices[AliasReg])) { DEBUG(dbgs() << "(alias " << TRI->getName(AliasReg) << " live)"); found = true; break; @@ -672,11 +679,11 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters( if (found) goto next_super_reg; } - + // Record that 'Reg' can be renamed to 'NewReg'. RenameMap.insert(std::pair(Reg, NewReg)); } - + // If we fall-out here, then every register in the group can be // renamed, as recorded in RenameMap. RenameOrder.erase(SuperRC); @@ -704,13 +711,13 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies( unsigned InsertPosIndex) { unsigned *KillIndices = State->GetKillIndices(); unsigned *DefIndices = State->GetDefIndices(); - std::multimap& + std::multimap& RegRefs = State->GetRegRefs(); // The code below assumes that there is at least one instruction, // so just duck out immediately if the block is empty. if (SUnits.empty()) return 0; - + // For each regclass the next register to use for renaming. RenameOrderType RenameOrder; @@ -729,17 +736,17 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies( if (CriticalPathSet.any()) { for (unsigned i = 0, e = SUnits.size(); i != e; ++i) { SUnit *SU = &SUnits[i]; - if (!CriticalPathSU || - ((SU->getDepth() + SU->Latency) > + if (!CriticalPathSU || + ((SU->getDepth() + SU->Latency) > (CriticalPathSU->getDepth() + CriticalPathSU->Latency))) { CriticalPathSU = SU; } } - + CriticalPathMI = CriticalPathSU->getInstr(); } -#ifndef NDEBUG +#ifndef NDEBUG DEBUG(dbgs() << "\n===== Aggressive anti-dependency breaking\n"); DEBUG(dbgs() << "Available regs:"); for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) { @@ -766,7 +773,7 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies( // Process the defs in MI... PrescanInstruction(MI, Count, PassthruRegs); - + // The dependence edges that represent anti- and output- // dependencies that are candidates for breaking. std::vector Edges; @@ -779,7 +786,7 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies( if (MI == CriticalPathMI) { CriticalPathSU = CriticalPathStep(CriticalPathSU); CriticalPathMI = (CriticalPathSU) ? CriticalPathSU->getInstr() : 0; - } else { + } else { ExcludeRegs = &CriticalPathSet; } @@ -790,14 +797,14 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies( for (unsigned i = 0, e = Edges.size(); i != e; ++i) { SDep *Edge = Edges[i]; SUnit *NextSU = Edge->getSUnit(); - + if ((Edge->getKind() != SDep::Anti) && (Edge->getKind() != SDep::Output)) continue; - + unsigned AntiDepReg = Edge->getReg(); DEBUG(dbgs() << "\tAntidep reg: " << TRI->getName(AntiDepReg)); assert(AntiDepReg != 0 && "Anti-dependence on reg0?"); - + if (!AllocatableSet.test(AntiDepReg)) { // Don't break anti-dependencies on non-allocatable registers. DEBUG(dbgs() << " (non-allocatable)\n"); @@ -816,12 +823,13 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies( } else { // No anti-dep breaking for implicit deps MachineOperand *AntiDepOp = MI->findRegisterDefOperand(AntiDepReg); - assert(AntiDepOp != NULL && "Can't find index for defined register operand"); + assert(AntiDepOp != NULL && + "Can't find index for defined register operand"); if ((AntiDepOp == NULL) || AntiDepOp->isImplicit()) { DEBUG(dbgs() << " (implicit)\n"); continue; } - + // If the SUnit has other dependencies on the SUnit that // it anti-depends on, don't bother breaking the // anti-dependency since those edges would prevent such @@ -847,58 +855,59 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies( DEBUG(dbgs() << " (real dependency)\n"); AntiDepReg = 0; break; - } else if ((P->getSUnit() != NextSU) && - (P->getKind() == SDep::Data) && + } else if ((P->getSUnit() != NextSU) && + (P->getKind() == SDep::Data) && (P->getReg() == AntiDepReg)) { DEBUG(dbgs() << " (other dependency)\n"); AntiDepReg = 0; break; } } - + if (AntiDepReg == 0) continue; } - + assert(AntiDepReg != 0); if (AntiDepReg == 0) continue; - + // Determine AntiDepReg's register group. const unsigned GroupIndex = State->GetGroup(AntiDepReg); if (GroupIndex == 0) { DEBUG(dbgs() << " (zero group)\n"); continue; } - + DEBUG(dbgs() << '\n'); - + // Look for a suitable register to use to break the anti-dependence. std::map RenameMap; if (FindSuitableFreeRegisters(GroupIndex, RenameOrder, RenameMap)) { DEBUG(dbgs() << "\tBreaking anti-dependence edge on " << TRI->getName(AntiDepReg) << ":"); - + // Handle each group register... for (std::map::iterator S = RenameMap.begin(), E = RenameMap.end(); S != E; ++S) { unsigned CurrReg = S->first; unsigned NewReg = S->second; - - DEBUG(dbgs() << " " << TRI->getName(CurrReg) << "->" << - TRI->getName(NewReg) << "(" << + + DEBUG(dbgs() << " " << TRI->getName(CurrReg) << "->" << + TRI->getName(NewReg) << "(" << RegRefs.count(CurrReg) << " refs)"); - + // Update the references to the old register CurrReg to // refer to the new register NewReg. - std::pair::iterator, + std::pair::iterator, std::multimap::iterator> + AggressiveAntiDepState::RegisterReference>::iterator> Range = RegRefs.equal_range(CurrReg); - for (std::multimap::iterator + for (std::multimap::iterator Q = Range.first, QE = Range.second; Q != QE; ++Q) { Q->second.Operand->setReg(NewReg); } - + // We just went back in time and modified history; the // liveness information for CurrReg is now inconsistent. Set // the state as if it were dead. @@ -906,7 +915,7 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies( RegRefs.erase(NewReg); DefIndices[NewReg] = DefIndices[CurrReg]; KillIndices[NewReg] = KillIndices[CurrReg]; - + State->UnionGroups(CurrReg, 0); RegRefs.erase(CurrReg); DefIndices[CurrReg] = KillIndices[CurrReg]; @@ -915,7 +924,7 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies( (DefIndices[CurrReg] == ~0u)) && "Kill and Def maps aren't consistent for AntiDepReg!"); } - + ++Broken; DEBUG(dbgs() << '\n'); } @@ -924,6 +933,6 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies( ScanInstruction(MI, Count); } - + return Broken; } diff --git a/lib/CodeGen/AggressiveAntiDepBreaker.h b/lib/CodeGen/AggressiveAntiDepBreaker.h index d385a212c7..a62d68c2a8 100644 --- a/lib/CodeGen/AggressiveAntiDepBreaker.h +++ b/lib/CodeGen/AggressiveAntiDepBreaker.h @@ -30,7 +30,7 @@ #include namespace llvm { - /// Class AggressiveAntiDepState + /// Class AggressiveAntiDepState /// Contains all the state necessary for anti-dep breaking. class AggressiveAntiDepState { public: @@ -54,27 +54,27 @@ namespace llvm { /// is the parent of a group, or point to another node to indicate /// that it is a member of the same group as that node. std::vector GroupNodes; - + /// GroupNodeIndices - For each register, the index of the GroupNode /// currently representing the group that the register belongs to. /// Register 0 is always represented by the 0 group, a group /// composed of registers that are not eligible for anti-aliasing. unsigned GroupNodeIndices[TargetRegisterInfo::FirstVirtualRegister]; - + /// RegRefs - Map registers to all their references within a live range. std::multimap RegRefs; - + /// KillIndices - The index of the most recent kill (proceding bottom-up), /// or ~0u if the register is not live. unsigned KillIndices[TargetRegisterInfo::FirstVirtualRegister]; - + /// DefIndices - The index of the most recent complete def (proceding bottom /// up), or ~0u if the register is live. unsigned DefIndices[TargetRegisterInfo::FirstVirtualRegister]; public: AggressiveAntiDepState(const unsigned TargetRegs, MachineBasicBlock *BB); - + /// GetKillIndices - Return the kill indices. unsigned *GetKillIndices() { return KillIndices; } @@ -87,13 +87,14 @@ namespace llvm { // GetGroup - Get the group for a register. The returned value is // the index of the GroupNode representing the group. unsigned GetGroup(unsigned Reg); - + // GetGroupRegs - Return a vector of the registers belonging to a // group. If RegRefs is non-NULL then only included referenced registers. void GetGroupRegs( unsigned Group, std::vector &Regs, - std::multimap *RegRefs); + std::multimap *RegRefs); // UnionGroups - Union Reg1's and Reg2's groups to form a new // group. Return the index of the GroupNode representing the @@ -110,7 +111,7 @@ namespace llvm { }; - /// Class AggressiveAntiDepBreaker + /// Class AggressiveAntiDepBreaker class AggressiveAntiDepBreaker : public AntiDepBreaker { MachineFunction& MF; MachineRegisterInfo &MRI; @@ -130,14 +131,15 @@ namespace llvm { AggressiveAntiDepState *State; public: - AggressiveAntiDepBreaker(MachineFunction& MFi, + AggressiveAntiDepBreaker(MachineFunction& MFi, TargetSubtarget::RegClassVector& CriticalPathRCs); ~AggressiveAntiDepBreaker(); - + /// Start - Initialize anti-dep breaking for a new basic block. void StartBlock(MachineBasicBlock *BB); - /// BreakAntiDependencies - Identifiy anti-dependencies along the critical path + /// BreakAntiDependencies - Identifiy anti-dependencies along the critical + /// path /// of the ScheduleDAG and break them by renaming registers. /// unsigned BreakAntiDependencies(std::vector& SUnits, @@ -160,7 +162,7 @@ namespace llvm { /// IsImplicitDefUse - Return true if MO represents a register /// that is both implicitly used and defined in MI bool IsImplicitDefUse(MachineInstr *MI, MachineOperand& MO); - + /// GetPassthruRegs - If MI implicitly def/uses a register, then /// return that register and all subregisters. void GetPassthruRegs(MachineInstr *MI, std::set& PassthruRegs); diff --git a/lib/CodeGen/CriticalAntiDepBreaker.cpp b/lib/CodeGen/CriticalAntiDepBreaker.cpp index 12584bdadb..e5d68a6cb8 100644 --- a/lib/CodeGen/CriticalAntiDepBreaker.cpp +++ b/lib/CodeGen/CriticalAntiDepBreaker.cpp @@ -290,7 +290,8 @@ void CriticalAntiDepBreaker::ScanInstruction(MachineInstr *MI, unsigned CriticalAntiDepBreaker::findSuitableFreeRegister(unsigned AntiDepReg, unsigned LastNewReg, - const TargetRegisterClass *RC) { + const TargetRegisterClass *RC) +{ for (TargetRegisterClass::iterator R = RC->allocation_order_begin(MF), RE = RC->allocation_order_end(MF); R != RE; ++R) { unsigned NewReg = *R; @@ -302,10 +303,10 @@ CriticalAntiDepBreaker::findSuitableFreeRegister(unsigned AntiDepReg, if (NewReg == LastNewReg) continue; // If NewReg is dead and NewReg's most recent def is not before // AntiDepReg's kill, it's safe to replace AntiDepReg with NewReg. - assert(((KillIndices[AntiDepReg] == ~0u) != (DefIndices[AntiDepReg] == ~0u)) && - "Kill and Def maps aren't consistent for AntiDepReg!"); - assert(((KillIndices[NewReg] == ~0u) != (DefIndices[NewReg] == ~0u)) && - "Kill and Def maps aren't consistent for NewReg!"); + assert(((KillIndices[AntiDepReg] == ~0u) != (DefIndices[AntiDepReg] == ~0u)) + && "Kill and Def maps aren't consistent for AntiDepReg!"); + assert(((KillIndices[NewReg] == ~0u) != (DefIndices[NewReg] == ~0u)) + && "Kill and Def maps aren't consistent for NewReg!"); if (KillIndices[NewReg] != ~0u || Classes[NewReg] == reinterpret_cast(-1) || KillIndices[AntiDepReg] > DefIndices[NewReg]) diff --git a/lib/CodeGen/CriticalAntiDepBreaker.h b/lib/CodeGen/CriticalAntiDepBreaker.h index 496888d45f..3740667193 100644 --- a/lib/CodeGen/CriticalAntiDepBreaker.h +++ b/lib/CodeGen/CriticalAntiDepBreaker.h @@ -64,11 +64,12 @@ namespace llvm { public: CriticalAntiDepBreaker(MachineFunction& MFi); ~CriticalAntiDepBreaker(); - + /// Start - Initialize anti-dep breaking for a new basic block. void StartBlock(MachineBasicBlock *BB); - /// BreakAntiDependencies - Identifiy anti-dependencies along the critical path + /// BreakAntiDependencies - Identifiy anti-dependencies along the critical + /// path /// of the ScheduleDAG and break them by renaming registers. /// unsigned BreakAntiDependencies(std::vector& SUnits, -- cgit v1.2.3