From 62131ab28074e0ef5545775c248c2905d09e498c Mon Sep 17 00:00:00 2001 From: Bill Wendling Date: Wed, 22 May 2013 17:23:54 +0000 Subject: Merging r182486: ------------------------------------------------------------------------ r182486 | d0k | 2013-05-22 10:01:12 -0700 (Wed, 22 May 2013) | 3 lines X86: When expanding PCMPGTQ to PCMPGTD we always want to compare the lower halves as unsigned. Take #2 on fixing PR15977. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182489 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86ISelLowering.cpp | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) (limited to 'lib') diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 9d0afbe237..f69f5d85f7 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -9347,12 +9347,19 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget, Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1); // Since SSE has no unsigned integer comparisons, we need to flip the sign - // bits of the inputs before performing those operations. + // bits of the inputs before performing those operations. The lower + // compare is always unsigned. + SDValue SB; if (FlipSigns) { - SDValue SB = DAG.getConstant(0x80000000U, MVT::v4i32); - Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB); - Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB); + SB = DAG.getConstant(0x80000000U, MVT::v4i32); + } else { + SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32); + SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32); + SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, + Sign, Zero, Sign, Zero); } + Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB); + Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB); // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2)) SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1); -- cgit v1.2.3