From b76dfe06d9eb42a4b7ffbb02997a2a8eead4faa1 Mon Sep 17 00:00:00 2001
From: Jim Grosbach <grosbach@apple.com>
Date: Wed, 8 Dec 2010 22:50:19 +0000
Subject: Add operand encoding for Thumb2 addw SP + imm. rdar://8745434

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121305 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/ARM/ARMInstrThumb2.td | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

(limited to 'lib')

diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td
index 5a36797216..066e601ea7 100644
--- a/lib/Target/ARM/ARMInstrThumb2.td
+++ b/lib/Target/ARM/ARMInstrThumb2.td
@@ -1152,14 +1152,18 @@ def t2ADDrSPi   : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$sp, t2_so_imm:$imm),
   let Inst{19-16} = 0b1101; // Rn = sp
   let Inst{15} = 0;
 }
-def t2ADDrSPi12 : T2TwoRegImm<(outs GPR:$Rd), (ins GPR:$sp, imm0_4095:$imm),
+def t2ADDrSPi12 : T2I<(outs GPR:$Rd), (ins GPR:$sp, imm0_4095:$imm),
                        IIC_iALUi, "addw", "\t$Rd, $sp, $imm", []> {
+  bits<4> Rd;
+  bits<12> imm;
   let Inst{31-27} = 0b11110;
-  let Inst{25} = 1;
-  let Inst{24-21} = 0b0000;
-  let Inst{20} = 0; // The S bit.
+  let Inst{26} = imm{11};
+  let Inst{25-20} = 0b100000;
   let Inst{19-16} = 0b1101; // Rn = sp
   let Inst{15} = 0;
+  let Inst{14-12} = imm{10-8};
+  let Inst{11-8} = Rd;
+  let Inst{7-0} = imm{7-0};
 }
 
 // ADD r, sp, so_reg
-- 
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