From d5acbbf90b6f5e1f4d39ff1935071f79ba607cbd Mon Sep 17 00:00:00 2001 From: James Molloy Date: Wed, 30 Apr 2014 10:15:50 +0000 Subject: [ARM64] Simplify if condition. v2f32 and v4f32 were missed out of these conditions, so this is also a bugfix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207628 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM64/ARM64ISelLowering.cpp | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) (limited to 'lib') diff --git a/lib/Target/ARM64/ARM64ISelLowering.cpp b/lib/Target/ARM64/ARM64ISelLowering.cpp index 769bcf21ed..869efcb4d4 100644 --- a/lib/Target/ARM64/ARM64ISelLowering.cpp +++ b/lib/Target/ARM64/ARM64ISelLowering.cpp @@ -1678,13 +1678,9 @@ SDValue ARM64TargetLowering::LowerFormalArguments( RC = &ARM64::GPR64RegClass; else if (RegVT == MVT::f32) RC = &ARM64::FPR32RegClass; - else if (RegVT == MVT::f64 || RegVT == MVT::v1i64 || - RegVT == MVT::v1f64 || RegVT == MVT::v2i32 || - RegVT == MVT::v4i16 || RegVT == MVT::v8i8) + else if (RegVT == MVT::f64 || RegVT.is64BitVector()) RC = &ARM64::FPR64RegClass; - else if (RegVT == MVT::f128 ||RegVT == MVT::v2i64 || - RegVT == MVT::v4i32||RegVT == MVT::v8i16 || - RegVT == MVT::v16i8) + else if (RegVT == MVT::f128 || RegVT.is128BitVector()) RC = &ARM64::FPR128RegClass; else llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering"); -- cgit v1.2.3