From caab129cd19441817906ea5ca69e341e81c598e3 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Wed, 6 May 2009 18:25:01 +0000 Subject: Do not use register as base ptr of pre- and post- inc/dec load / store nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71098 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll (limited to 'test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll') diff --git a/test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll b/test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll new file mode 100644 index 0000000000..2bca6e62fc --- /dev/null +++ b/test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll @@ -0,0 +1,11 @@ +; RUN: llvm-as < %s | llc -mtriple=arm-linuxeabi-unknown-gnu -mattr=+v6 +; PR4166 + + %"byte[]" = type { i32, i8* } + %tango.time.Time.Time = type { i64 } + +define fastcc void @t() { +entry: + %tmp28 = call fastcc i1 null(i32* null, %"byte[]" undef, %"byte[]" undef, %tango.time.Time.Time* byval null) ; [#uses=0] + ret void +} -- cgit v1.2.3