From 5a02fc4b5fa0eba4d0875db710400a74ada3b15f Mon Sep 17 00:00:00 2001 From: Tim Northover Date: Thu, 23 May 2013 19:11:20 +0000 Subject: ARM: implement @llvm.readcyclecounter intrinsic This implements the @llvm.readcyclecounter intrinsic as the specific MRC instruction specified in the ARM manuals for CPUs with the Power Management extensions. Older CPUs had slightly different methods which may also have to be implemented eventually, but this should cover all v7 cases. rdar://problem/13939186 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182603 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/ARM/readcyclecounter.ll | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 test/CodeGen/ARM/readcyclecounter.ll (limited to 'test/CodeGen/ARM/readcyclecounter.ll') diff --git a/test/CodeGen/ARM/readcyclecounter.ll b/test/CodeGen/ARM/readcyclecounter.ll new file mode 100644 index 0000000000..db47ad355d --- /dev/null +++ b/test/CodeGen/ARM/readcyclecounter.ll @@ -0,0 +1,24 @@ +; RUN: llc -mtriple=armv7-none-linux-gnueabi < %s | FileCheck %s +; RUN: llc -mtriple=thumbv7-none-linux-gnueabi < %s | FileCheck %s +; RUN: llc -mtriple=armv7-none-linux-gnueabi -mattr=-perfmon < %s | FileCheck %s --check-prefix=CHECK-NO-PERFMON +; RUN: llc -mtriple=armv6-none-linux-gnueabi < %s | FileCheck %s --check-prefix=CHECK-NO-PERFMON + +; The performance monitor we're looking for is an ARMv7 extension. It should be +; possible to disable it, but realistically present on at least every v7-A +; processor (but not on v6, at least by default). + +declare i64 @llvm.readcyclecounter() + +define i64 @get_count() { + %val = call i64 @llvm.readcyclecounter() + ret i64 %val + + ; As usual, exact registers only sort of matter but the cycle-count had better + ; end up in r0 in the end. + +; CHECK: mrc p15, #0, r0, c9, c13, #0 +; CHECK: {{movs?}} r1, #0 + +; CHECK-NO-PERFMON: {{movs?}} r0, #0 +; CHECK-NO-PERFMON: {{movs?}} r1, #0 +} -- cgit v1.2.3