From 8239daf7c83a65a189c352cce3191cdc3bbfe151 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Wed, 3 Nov 2010 00:45:17 +0000 Subject: Two sets of changes. Sorry they are intermingled. 1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to "optimize for latency". Call instructions don't have the right latency and this is more likely to use introduce spills. 2. Fix if-converter cost function. For ARM, it should use instruction latencies, not # of micro-ops since multi-latency instructions is completely executed even when the predicate is false. Also, some instruction will be "slower" when they are predicated due to the register def becoming implicit input. rdar://8598427 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118135 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/ARM/reg_sequence.ll | 1 - 1 file changed, 1 deletion(-) (limited to 'test/CodeGen/ARM/reg_sequence.ll') diff --git a/test/CodeGen/ARM/reg_sequence.ll b/test/CodeGen/ARM/reg_sequence.ll index 390955472e..24eb3a88fb 100644 --- a/test/CodeGen/ARM/reg_sequence.ll +++ b/test/CodeGen/ARM/reg_sequence.ll @@ -271,7 +271,6 @@ define arm_aapcs_vfpcc i32 @t10() nounwind { entry: ; CHECK: t10: ; CHECK: vmov.i32 q9, #0x3F000000 -; CHECK: vmov d0, d17 ; CHECK: vmla.f32 q8, q8, d0[0] %0 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1] %1 = insertelement <4 x float> %0, float undef, i32 1 ; <<4 x float>> [#uses=1] -- cgit v1.2.3