From 7d24705f6538688937f571961d41c7bb2985c7e3 Mon Sep 17 00:00:00 2001 From: Bob Wilson Date: Fri, 8 Oct 2010 06:15:13 +0000 Subject: Change register allocation order for ARM VFP and NEON registers to put the callee-saved registers at the end of the lists. Also prefer to avoid using the low registers that are in register subclasses required by certain instructions, so that those registers will more likely be available when needed. This change makes a huge improvement in spilling in some cases. Thanks to Jakob for helping me realize the problem. Most of this patch is fixing the testsuite. There are quite a few places where we're checking for specific registers. I changed those to wildcards in places where that doesn't weaken the tests. The spill-q.ll and thumb2-spill-q.ll tests stopped spilling with this change, so I added a bunch of live values to force spills on those tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116055 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/ARM/vld2.ll | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'test/CodeGen/ARM/vld2.ll') diff --git a/test/CodeGen/ARM/vld2.ll b/test/CodeGen/ARM/vld2.ll index fe99dd5025..3fdd7b7aa8 100644 --- a/test/CodeGen/ARM/vld2.ll +++ b/test/CodeGen/ARM/vld2.ll @@ -14,7 +14,7 @@ define <8 x i8> @vld2i8(i8* %A) nounwind { ;CHECK: vld2i8: ;Check the alignment value. Max for this instruction is 128 bits: -;CHECK: vld2.8 {d0, d1}, [r0, :64] +;CHECK: vld2.8 {d16, d17}, [r0, :64] %tmp1 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2.v8i8(i8* %A, i32 8) %tmp2 = extractvalue %struct.__neon_int8x8x2_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp1, 1 @@ -25,7 +25,7 @@ define <8 x i8> @vld2i8(i8* %A) nounwind { define <4 x i16> @vld2i16(i16* %A) nounwind { ;CHECK: vld2i16: ;Check the alignment value. Max for this instruction is 128 bits: -;CHECK: vld2.16 {d0, d1}, [r0, :128] +;CHECK: vld2.16 {d16, d17}, [r0, :128] %tmp0 = bitcast i16* %A to i8* %tmp1 = call %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2.v4i16(i8* %tmp0, i32 32) %tmp2 = extractvalue %struct.__neon_int16x4x2_t %tmp1, 0 @@ -59,7 +59,7 @@ define <2 x float> @vld2f(float* %A) nounwind { define <1 x i64> @vld2i64(i64* %A) nounwind { ;CHECK: vld2i64: ;Check the alignment value. Max for this instruction is 128 bits: -;CHECK: vld1.64 {d0, d1}, [r0, :128] +;CHECK: vld1.64 {d16, d17}, [r0, :128] %tmp0 = bitcast i64* %A to i8* %tmp1 = call %struct.__neon_int64x1x2_t @llvm.arm.neon.vld2.v1i64(i8* %tmp0, i32 32) %tmp2 = extractvalue %struct.__neon_int64x1x2_t %tmp1, 0 @@ -71,7 +71,7 @@ define <1 x i64> @vld2i64(i64* %A) nounwind { define <16 x i8> @vld2Qi8(i8* %A) nounwind { ;CHECK: vld2Qi8: ;Check the alignment value. Max for this instruction is 256 bits: -;CHECK: vld2.8 {d0, d1, d2, d3}, [r0, :64] +;CHECK: vld2.8 {d16, d17, d18, d19}, [r0, :64] %tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8(i8* %A, i32 8) %tmp2 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 1 @@ -82,7 +82,7 @@ define <16 x i8> @vld2Qi8(i8* %A) nounwind { define <8 x i16> @vld2Qi16(i16* %A) nounwind { ;CHECK: vld2Qi16: ;Check the alignment value. Max for this instruction is 256 bits: -;CHECK: vld2.16 {d0, d1, d2, d3}, [r0, :128] +;CHECK: vld2.16 {d16, d17, d18, d19}, [r0, :128] %tmp0 = bitcast i16* %A to i8* %tmp1 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2.v8i16(i8* %tmp0, i32 16) %tmp2 = extractvalue %struct.__neon_int16x8x2_t %tmp1, 0 @@ -94,7 +94,7 @@ define <8 x i16> @vld2Qi16(i16* %A) nounwind { define <4 x i32> @vld2Qi32(i32* %A) nounwind { ;CHECK: vld2Qi32: ;Check the alignment value. Max for this instruction is 256 bits: -;CHECK: vld2.32 {d0, d1, d2, d3}, [r0, :256] +;CHECK: vld2.32 {d16, d17, d18, d19}, [r0, :256] %tmp0 = bitcast i32* %A to i8* %tmp1 = call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8* %tmp0, i32 64) %tmp2 = extractvalue %struct.__neon_int32x4x2_t %tmp1, 0 -- cgit v1.2.3