From c692cb77aaa8b16bcc7fe0c70d47adce94c43911 Mon Sep 17 00:00:00 2001 From: Bob Wilson Date: Fri, 21 Aug 2009 20:54:19 +0000 Subject: Match VTRN, VZIP, and VUZP shuffles. Restore the tests for these operations, now using shuffles instead of intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79673 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/ARM/vtrn.ll | 99 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 99 insertions(+) create mode 100644 test/CodeGen/ARM/vtrn.ll (limited to 'test/CodeGen/ARM/vtrn.ll') diff --git a/test/CodeGen/ARM/vtrn.ll b/test/CodeGen/ARM/vtrn.ll new file mode 100644 index 0000000000..96dfb3ede4 --- /dev/null +++ b/test/CodeGen/ARM/vtrn.ll @@ -0,0 +1,99 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s + +%struct.__builtin_neon_v8qi2 = type { <8 x i8>, <8 x i8> } +%struct.__builtin_neon_v4hi2 = type { <4 x i16>, <4 x i16> } +%struct.__builtin_neon_v2si2 = type { <2 x i32>, <2 x i32> } +%struct.__builtin_neon_v2sf2 = type { <2 x float>, <2 x float> } + +%struct.__builtin_neon_v16qi2 = type { <16 x i8>, <16 x i8> } +%struct.__builtin_neon_v8hi2 = type { <8 x i16>, <8 x i16> } +%struct.__builtin_neon_v4si2 = type { <4 x i32>, <4 x i32> } +%struct.__builtin_neon_v4sf2 = type { <4 x float>, <4 x float> } + +define <8 x i8> @vtrni8(<8 x i8>* %A, <8 x i8>* %B) nounwind { +;CHECK: vtrni8: +;CHECK: vtrn.8 + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> + %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> + %tmp5 = add <8 x i8> %tmp3, %tmp4 + ret <8 x i8> %tmp5 +} + +define <4 x i16> @vtrni16(<4 x i16>* %A, <4 x i16>* %B) nounwind { +;CHECK: vtrni16: +;CHECK: vtrn.16 + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> + %tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> + %tmp5 = add <4 x i16> %tmp3, %tmp4 + ret <4 x i16> %tmp5 +} + +define <2 x i32> @vtrni32(<2 x i32>* %A, <2 x i32>* %B) nounwind { +;CHECK: vtrni32: +;CHECK: vtrn.32 + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> + %tmp4 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> + %tmp5 = add <2 x i32> %tmp3, %tmp4 + ret <2 x i32> %tmp5 +} + +define <2 x float> @vtrnf(<2 x float>* %A, <2 x float>* %B) nounwind { +;CHECK: vtrnf: +;CHECK: vtrn.32 + %tmp1 = load <2 x float>* %A + %tmp2 = load <2 x float>* %B + %tmp3 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <2 x i32> + %tmp4 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <2 x i32> + %tmp5 = add <2 x float> %tmp3, %tmp4 + ret <2 x float> %tmp5 +} + +define <16 x i8> @vtrnQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { +;CHECK: vtrnQi8: +;CHECK: vtrn.8 + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> + %tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> + %tmp5 = add <16 x i8> %tmp3, %tmp4 + ret <16 x i8> %tmp5 +} + +define <8 x i16> @vtrnQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { +;CHECK: vtrnQi16: +;CHECK: vtrn.16 + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> + %tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> + %tmp5 = add <8 x i16> %tmp3, %tmp4 + ret <8 x i16> %tmp5 +} + +define <4 x i32> @vtrnQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { +;CHECK: vtrnQi32: +;CHECK: vtrn.32 + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> + %tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> + %tmp5 = add <4 x i32> %tmp3, %tmp4 + ret <4 x i32> %tmp5 +} + +define <4 x float> @vtrnQf(<4 x float>* %A, <4 x float>* %B) nounwind { +;CHECK: vtrnQf: +;CHECK: vtrn.32 + %tmp1 = load <4 x float>* %A + %tmp2 = load <4 x float>* %B + %tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> + %tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> + %tmp5 = add <4 x float> %tmp3, %tmp4 + ret <4 x float> %tmp5 +} -- cgit v1.2.3