From a7c3cac87118c3e409a7fc889090c5ffe242985e Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Wed, 30 Oct 2013 13:51:01 +0000 Subject: [mips][msa] Combine binsri-like DAG of AND and OR into equivalent VSELECT (or (and $a, $mask), (and $b, $inverse_mask)) => (vselect $mask, $a, $b). where $mask is a constant splat. This allows bitwise operations to make use of bsel. It's also a stepping stone towards matching bins[lr], and bins[lr]i from normal IR. Two sets of similar tests have been added in this commit. The bsel_* functions test the case where binsri cannot be used. The binsr_*_i functions will start to use the binsri instruction in the next commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193682 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/Mips/msa/bitwise.ll | 164 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 164 insertions(+) (limited to 'test/CodeGen/Mips') diff --git a/test/CodeGen/Mips/msa/bitwise.ll b/test/CodeGen/Mips/msa/bitwise.ll index f5da9f247c..a606fdfb85 100644 --- a/test/CodeGen/Mips/msa/bitwise.ll +++ b/test/CodeGen/Mips/msa/bitwise.ll @@ -972,6 +972,170 @@ define void @ctlz_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind { ; CHECK: .size ctlz_v2i64 } +define void @bsel_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind { + ; CHECK: bsel_v16i8: + + %1 = load <16 x i8>* %a + ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5) + %2 = load <16 x i8>* %b + ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6) + %3 = and <16 x i8> %1, + %4 = and <16 x i8> %2, + %5 = or <16 x i8> %3, %4 + ; CHECK-DAG: ldi.b [[R3:\$w[0-9]+]], 6 + ; CHECK-DAG: bsel.v [[R3]], [[R2]], [[R1]] + store <16 x i8> %5, <16 x i8>* %c + ; CHECK-DAG: st.b [[R3]], 0($4) + + ret void + ; CHECK: .size bsel_v16i8 +} + +define void @bsel_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind { + ; CHECK: bsel_v8i16: + + %1 = load <8 x i16>* %a + ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5) + %2 = load <8 x i16>* %b + ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6) + %3 = and <8 x i16> %1, + %4 = and <8 x i16> %2, + %5 = or <8 x i16> %3, %4 + ; CHECK-DAG: ldi.h [[R3:\$w[0-9]+]], 6 + ; CHECK-DAG: bsel.v [[R3]], [[R2]], [[R1]] + store <8 x i16> %5, <8 x i16>* %c + ; CHECK-DAG: st.h [[R3]], 0($4) + + ret void + ; CHECK: .size bsel_v8i16 +} + +define void @bsel_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind { + ; CHECK: bsel_v4i32: + + %1 = load <4 x i32>* %a + ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) + %2 = load <4 x i32>* %b + ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) + %3 = and <4 x i32> %1, + %4 = and <4 x i32> %2, + %5 = or <4 x i32> %3, %4 + ; CHECK-DAG: ldi.w [[R3:\$w[0-9]+]], 6 + ; CHECK-DAG: bsel.v [[R3]], [[R2]], [[R1]] + store <4 x i32> %5, <4 x i32>* %c + ; CHECK-DAG: st.w [[R3]], 0($4) + + ret void + ; CHECK: .size bsel_v4i32 +} + +define void @bsel_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind { + ; CHECK: bsel_v2i64: + + %1 = load <2 x i64>* %a + ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) + %2 = load <2 x i64>* %b + ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) + %3 = and <2 x i64> %1, + %4 = and <2 x i64> %2, + %5 = or <2 x i64> %3, %4 + ; CHECK-DAG: ldi.d [[R3:\$w[0-9]+]], 6 + ; CHECK-DAG: bsel.v [[R3]], [[R2]], [[R1]] + store <2 x i64> %5, <2 x i64>* %c + ; CHECK-DAG: st.d [[R3]], 0($4) + + ret void + ; CHECK: .size bsel_v2i64 +} + +define void @binsr_v16i8_i(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind { + ; CHECK: binsr_v16i8_i: + + %1 = load <16 x i8>* %a + ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5) + %2 = load <16 x i8>* %b + ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6) + %3 = and <16 x i8> %1, + %4 = and <16 x i8> %2, + %5 = or <16 x i8> %3, %4 + ; CHECK-DAG: ldi.b [[R3:\$w[0-9]+]], 3 + ; CHECK-DAG: bsel.v [[R3]], [[R2]], [[R1]] + store <16 x i8> %5, <16 x i8>* %c + ; CHECK-DAG: st.b [[R3]], 0($4) + + ret void + ; CHECK: .size binsr_v16i8_i +} + +define void @binsr_v8i16_i(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind { + ; CHECK: binsr_v8i16_i: + + %1 = load <8 x i16>* %a + ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5) + %2 = load <8 x i16>* %b + ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6) + %3 = and <8 x i16> %1, + %4 = and <8 x i16> %2, + %5 = or <8 x i16> %3, %4 + ; CHECK-DAG: ldi.h [[R3:\$w[0-9]+]], 3 + ; CHECK-DAG: bsel.v [[R3]], [[R2]], [[R1]] + store <8 x i16> %5, <8 x i16>* %c + ; CHECK-DAG: st.h [[R3]], 0($4) + + ret void + ; CHECK: .size binsr_v8i16_i +} + +define void @binsr_v4i32_i(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind { + ; CHECK: binsr_v4i32_i: + + %1 = load <4 x i32>* %a + ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) + %2 = load <4 x i32>* %b + ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) + %3 = and <4 x i32> %1, + %4 = and <4 x i32> %2, + %5 = or <4 x i32> %3, %4 + ; CHECK-DAG: ldi.w [[R3:\$w[0-9]+]], 3 + ; CHECK-DAG: bsel.v [[R3]], [[R2]], [[R1]] + store <4 x i32> %5, <4 x i32>* %c + ; CHECK-DAG: st.w [[R3]], 0($4) + + ret void + ; CHECK: .size binsr_v4i32_i +} + +define void @binsr_v2i64_i(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind { + ; CHECK: binsr_v2i64_i: + + %1 = load <2 x i64>* %a + ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) + %2 = load <2 x i64>* %b + ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) + %3 = and <2 x i64> %1, + %4 = and <2 x i64> %2, + %5 = or <2 x i64> %3, %4 + ; CHECK-DAG: ldi.d [[R3:\$w[0-9]+]], 3 + ; CHECK-DAG: bsel.v [[R3]], [[R2]], [[R1]] + store <2 x i64> %5, <2 x i64>* %c + ; CHECK-DAG: st.d [[R3]], 0($4) + + ret void + ; CHECK: .size binsr_v2i64_i +} + declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %val) declare <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %val) declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %val) -- cgit v1.2.3