From f9a5e40b90e5a98cfae5c0f8a42eedd71c849dbc Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Thu, 17 Oct 2013 11:16:57 +0000 Subject: Replace sra with srl if a single sign bit is required E.g. (and (sra (i32 x) 31) 2) -> (and (srl (i32 x) 30) 2). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192884 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/PowerPC/rlwimi-and.ll | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'test/CodeGen/PowerPC') diff --git a/test/CodeGen/PowerPC/rlwimi-and.ll b/test/CodeGen/PowerPC/rlwimi-and.ll index e20a13fec0..7963249ddf 100644 --- a/test/CodeGen/PowerPC/rlwimi-and.ll +++ b/test/CodeGen/PowerPC/rlwimi-and.ll @@ -28,12 +28,11 @@ codeRepl17: ; preds = %codeRepl4 store i16 %rvml38.sroa.0.0.insert.insert, i16* undef, align 2 unreachable +; FIXME: the SLWI could be folded into the RLWIMI to give a rotate of 8. ; CHECK: @test -; CHECK-DAG: slwi [[R1:[0-9]+]], -; CHECK-DAG: rlwinm [[R2:[0-9]+]], -; CHECK-DAG: srawi [[R3:[0-9]+]], [[R1]] -; CHECK-DAG: rlwinm [[R4:[0-9]+]], [[R3]], 0, 23, 23 -; CHECK: rlwimi [[R4]], [[R2]], 0, +; CHECK-DAG: slwi [[R1:[0-9]+]], {{[0-9]+}}, 31 +; CHECK-DAG: rlwinm [[R2:[0-9]+]], {{[0-9]+}}, 0, 31, 31 +; CHECK: rlwimi [[R2]], [[R1]], 9, 23, 23 codeRepl29: ; preds = %codeRepl1 unreachable -- cgit v1.2.3