From 65ddcfa8c1c05aeecd9d4fb062bb121e376aaceb Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Fri, 23 Aug 2013 11:18:53 +0000 Subject: [SystemZ] Prefer LHI;ST... over LAY;MV... If we had a store of an integer to memory, and the integer and store size were suitable for a form of MV..., we used MV... no matter what. We could then have sequences like: lay %r2, 0(%r3,%r4) mvi 0(%r2), 4 In these cases it seems better to force the constant into a register and use a normal store: lhi %r2, 4 stc %r2, 0(%r3, %r4) since %r2 is more likely to be hoisted and is easier to rematerialize. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189098 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/SystemZ/alloca-02.ll | 15 +++++++++------ test/CodeGen/SystemZ/frame-13.ll | 11 +++++------ test/CodeGen/SystemZ/int-const-03.ll | 12 ++++++------ test/CodeGen/SystemZ/int-const-04.ll | 20 ++++++++++---------- test/CodeGen/SystemZ/int-const-05.ll | 19 +++++++++---------- test/CodeGen/SystemZ/int-const-06.ll | 20 ++++++++++---------- 6 files changed, 49 insertions(+), 48 deletions(-) (limited to 'test/CodeGen/SystemZ') diff --git a/test/CodeGen/SystemZ/alloca-02.ll b/test/CodeGen/SystemZ/alloca-02.ll index b6ed7f7741..b5787b1023 100644 --- a/test/CodeGen/SystemZ/alloca-02.ll +++ b/test/CodeGen/SystemZ/alloca-02.ll @@ -21,18 +21,21 @@ define i64 @f1(i64 %length, i64 %index) { ; ; CHECK-C-LABEL: f1: ; CHECK-C: lgr %r15, [[ADDR:%r[1-5]]] -; CHECK-C: la [[TMP:%r[1-5]]], 160(%r3,[[ADDR]]) -; CHECK-C: mvi 0([[TMP]]), 2 +; CHECK-C-DAG: la %r2, 160([[ADDR]]) +; CHECK-C-DAG: lhi [[TMP:%r[0-5]]], 2 +; CHECK-C: stc [[TMP]], 0({{%r3,%r2|%r2,%r3}}) ; ; CHECK-D-LABEL: f1: ; CHECK-D: lgr %r15, [[ADDR:%r[1-5]]] -; CHECK-D: la [[TMP:%r[1-5]]], 160(%r3,[[ADDR]]) -; CHECK-D: mvi 4095([[TMP]]), 3 +; CHECK-D-DAG: la %r2, 160([[ADDR]]) +; CHECK-D-DAG: lhi [[TMP:%r[0-5]]], 3 +; CHECK-D: stc [[TMP]], 4095({{%r3,%r2|%r2,%r3}}) ; ; CHECK-E-LABEL: f1: ; CHECK-E: lgr %r15, [[ADDR:%r[1-5]]] -; CHECK-E: la [[TMP:%r[1-5]]], 160(%r3,[[ADDR]]) -; CHECK-E: mviy 4096([[TMP]]), 4 +; CHECK-E-DAG: la %r2, 160([[ADDR]]) +; CHECK-E-DAG: lhi [[TMP:%r[0-5]]], 4 +; CHECK-E: stcy [[TMP]], 4096({{%r3,%r2|%r2,%r3}}) %a = alloca i8, i64 %length store volatile i8 0, i8 *%a %b = getelementptr i8 *%a, i64 4095 diff --git a/test/CodeGen/SystemZ/frame-13.ll b/test/CodeGen/SystemZ/frame-13.ll index 1d38354269..60bff508d9 100644 --- a/test/CodeGen/SystemZ/frame-13.ll +++ b/test/CodeGen/SystemZ/frame-13.ll @@ -182,17 +182,16 @@ define void @f8() { } ; Check a case where the original displacement is out of range. The backend -; should force an LAY from the outset. We don't yet do any kind of anchor -; optimization, so there should be no offset on the MVHI itself. +; should force STY to be used instead. define void @f9() { ; CHECK-NOFP-LABEL: f9: -; CHECK-NOFP: lay %r1, 12296(%r15) -; CHECK-NOFP: mvhi 0(%r1), 42 +; CHECK-NOFP: lhi [[TMP:%r[0-5]]], 42 +; CHECK-NOFP: sty [[TMP]], 12296(%r15) ; CHECK-NOFP: br %r14 ; ; CHECK-FP-LABEL: f9: -; CHECK-FP: lay %r1, 12296(%r11) -; CHECK-FP: mvhi 0(%r1), 42 +; CHECK-FP: lhi [[TMP:%r[0-5]]], 42 +; CHECK-FP: sty [[TMP]], 12296(%r11) ; CHECK-FP: br %r14 %region1 = alloca [2006 x i32], align 8 %region2 = alloca [2006 x i32], align 8 diff --git a/test/CodeGen/SystemZ/int-const-03.ll b/test/CodeGen/SystemZ/int-const-03.ll index 78db9637e4..af1cef2c13 100644 --- a/test/CodeGen/SystemZ/int-const-03.ll +++ b/test/CodeGen/SystemZ/int-const-03.ll @@ -139,11 +139,11 @@ define void @f14(i8 *%src) { ret void } -; Check that MVI does not allow an index +; Check that MVI does not allow an index. We prefer STC in that case. define void @f15(i64 %src, i64 %index) { ; CHECK-LABEL: f15: -; CHECK: agr %r2, %r3 -; CHECK: mvi 4095(%r2), 42 +; CHECK: lhi [[TMP:%r[0-5]]], 42 +; CHECK: stc [[TMP]], 4095({{%r2,%r3|%r3,%r2}} ; CHECK: br %r14 %add1 = add i64 %src, %index %add2 = add i64 %add1, 4095 @@ -152,11 +152,11 @@ define void @f15(i64 %src, i64 %index) { ret void } -; Check that MVIY does not allow an index +; Check that MVIY does not allow an index. We prefer STCY in that case. define void @f16(i64 %src, i64 %index) { ; CHECK-LABEL: f16: -; CHECK: agr %r2, %r3 -; CHECK: mviy 4096(%r2), 42 +; CHECK: lhi [[TMP:%r[0-5]]], 42 +; CHECK: stcy [[TMP]], 4096({{%r2,%r3|%r3,%r2}} ; CHECK: br %r14 %add1 = add i64 %src, %index %add2 = add i64 %add1, 4096 diff --git a/test/CodeGen/SystemZ/int-const-04.ll b/test/CodeGen/SystemZ/int-const-04.ll index c109faab20..aced50b560 100644 --- a/test/CodeGen/SystemZ/int-const-04.ll +++ b/test/CodeGen/SystemZ/int-const-04.ll @@ -75,34 +75,34 @@ define void @f8(i16 *%a) { ret void } -; Check the next halfword up, which needs separate address logic. -; Other sequences besides this one would be OK. +; Check the next halfword up, which is out of range. We prefer STHY +; in that case. define void @f9(i16 *%a) { ; CHECK-LABEL: f9: -; CHECK: aghi %r2, 4096 -; CHECK: mvhhi 0(%r2), 42 +; CHECK: lhi [[TMP:%r[0-5]]], 42 +; CHECK: sthy [[TMP]], 4096(%r2) ; CHECK: br %r14 %ptr = getelementptr i16 *%a, i64 2048 store i16 42, i16 *%ptr ret void } -; Check negative displacements, which also need separate address logic. +; Check negative displacements, for which we again prefer STHY. define void @f10(i16 *%a) { ; CHECK-LABEL: f10: -; CHECK: aghi %r2, -2 -; CHECK: mvhhi 0(%r2), 42 +; CHECK: lhi [[TMP:%r[0-5]]], 42 +; CHECK: sthy [[TMP]], -2(%r2) ; CHECK: br %r14 %ptr = getelementptr i16 *%a, i64 -1 store i16 42, i16 *%ptr ret void } -; Check that MVHHI does not allow an index +; Check that MVHHI does not allow an index. define void @f11(i64 %src, i64 %index) { ; CHECK-LABEL: f11: -; CHECK: agr %r2, %r3 -; CHECK: mvhhi 0(%r2), 42 +; CHECK: lhi [[TMP:%r[0-5]]], 42 +; CHECK: sth [[TMP]], 0({{%r2,%r3|%r3,%r2}}) ; CHECK: br %r14 %add = add i64 %src, %index %ptr = inttoptr i64 %add to i16 * diff --git a/test/CodeGen/SystemZ/int-const-05.ll b/test/CodeGen/SystemZ/int-const-05.ll index d0c8569149..98d6851c19 100644 --- a/test/CodeGen/SystemZ/int-const-05.ll +++ b/test/CodeGen/SystemZ/int-const-05.ll @@ -66,34 +66,33 @@ define void @f7(i32 *%a) { ret void } -; Check the next word up, which needs separate address logic. -; Other sequences besides this one would be OK. +; Check the next word up, which is out of range. We prefer STY in that case. define void @f8(i32 *%a) { ; CHECK-LABEL: f8: -; CHECK: aghi %r2, 4096 -; CHECK: mvhi 0(%r2), 42 +; CHECK: lhi [[TMP:%r[0-5]]], 42 +; CHECK: sty [[TMP]], 4096(%r2) ; CHECK: br %r14 %ptr = getelementptr i32 *%a, i64 1024 store i32 42, i32 *%ptr ret void } -; Check negative displacements, which also need separate address logic. +; Check negative displacements, for which we again prefer STY. define void @f9(i32 *%a) { ; CHECK-LABEL: f9: -; CHECK: aghi %r2, -4 -; CHECK: mvhi 0(%r2), 42 +; CHECK: lhi [[TMP:%r[0-5]]], 42 +; CHECK: sty [[TMP]], -4(%r2) ; CHECK: br %r14 %ptr = getelementptr i32 *%a, i64 -1 store i32 42, i32 *%ptr ret void } -; Check that MVHI does not allow an index +; Check that MVHI does not allow an index. define void @f10(i64 %src, i64 %index) { ; CHECK-LABEL: f10: -; CHECK: agr %r2, %r3 -; CHECK: mvhi 0(%r2), 42 +; CHECK: lhi [[TMP:%r[0-5]]], 42 +; CHECK: st [[TMP]], 0({{%r2,%r3|%r3,%r2}}) ; CHECK: br %r14 %add = add i64 %src, %index %ptr = inttoptr i64 %add to i32 * diff --git a/test/CodeGen/SystemZ/int-const-06.ll b/test/CodeGen/SystemZ/int-const-06.ll index 12a555c61e..cf07c665dd 100644 --- a/test/CodeGen/SystemZ/int-const-06.ll +++ b/test/CodeGen/SystemZ/int-const-06.ll @@ -66,34 +66,34 @@ define void @f7(i64 *%a) { ret void } -; Check the next doubleword up, which needs separate address logic. -; Other sequences besides this one would be OK. +; Check the next doubleword up, which is out of range. We prefer STG +; in that case. define void @f8(i64 *%a) { ; CHECK-LABEL: f8: -; CHECK: aghi %r2, 4096 -; CHECK: mvghi 0(%r2), 42 +; CHECK: lghi [[TMP:%r[0-5]]], 42 +; CHECK: stg [[TMP]], 4096(%r2) ; CHECK: br %r14 %ptr = getelementptr i64 *%a, i64 512 store i64 42, i64 *%ptr ret void } -; Check negative displacements, which also need separate address logic. +; Check negative displacements, for which we again prefer STG. define void @f9(i64 *%a) { ; CHECK-LABEL: f9: -; CHECK: aghi %r2, -8 -; CHECK: mvghi 0(%r2), 42 +; CHECK: lghi [[TMP:%r[0-5]]], 42 +; CHECK: stg [[TMP]], -8(%r2) ; CHECK: br %r14 %ptr = getelementptr i64 *%a, i64 -1 store i64 42, i64 *%ptr ret void } -; Check that MVGHI does not allow an index +; Check that MVGHI does not allow an index. define void @f10(i64 %src, i64 %index) { ; CHECK-LABEL: f10: -; CHECK: agr %r2, %r3 -; CHECK: mvghi 0(%r2), 42 +; CHECK: lghi [[TMP:%r[0-5]]], 42 +; CHECK: stg [[TMP]], 0({{%r2,%r3|%r3,%r2}}) ; CHECK: br %r14 %add = add i64 %src, %index %ptr = inttoptr i64 %add to i64 * -- cgit v1.2.3