From 86a735396ab4804a06e76d1b4ce49dbd44c35827 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Tue, 26 Nov 2013 10:58:52 +0000 Subject: Merging r195731: ------------------------------------------------------------------------ r195731 | rsandifo | 2013-11-26 10:53:16 +0000 (Tue, 26 Nov 2013) | 7 lines [SystemZ] Fix incorrect use of RISBG for a zero-extended right shift We would wrongly transform the testcase into the equivalent of an AND with 1. The problem was that, when testing whether the shifted-in bits of the right shift were significant, we used the width of the final zero-extended result rather than the width of the shifted value. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195736 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/SystemZ/risbg-01.ll | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'test/CodeGen/SystemZ') diff --git a/test/CodeGen/SystemZ/risbg-01.ll b/test/CodeGen/SystemZ/risbg-01.ll index 8a5d4874f6..a4d11fdae5 100644 --- a/test/CodeGen/SystemZ/risbg-01.ll +++ b/test/CodeGen/SystemZ/risbg-01.ll @@ -456,3 +456,17 @@ define i64 @f40(i64 %foo, i64 *%dest) { %and = and i64 %shl, 2147483647 ret i64 %and } + +; In this case the sign extension is converted to a pair of 32-bit shifts, +; which is then extended to 64 bits. We previously used the wrong bit size +; when testing whether the shifted-in bits of the shift right were significant. +define i64 @f41(i1 %x) { +; CHECK-LABEL: f41: +; CHECK: sll %r2, 31 +; CHECK: sra %r2, 31 +; CHECK: llgcr %r2, %r2 +; CHECK: br %r14 + %ext = sext i1 %x to i8 + %ext2 = zext i8 %ext to i64 + ret i64 %ext2 +} -- cgit v1.2.3