From c8d12eee12bbd0dca3def72d52e410eaf4e61b2d Mon Sep 17 00:00:00 2001 From: Nadav Rotem Date: Wed, 11 Jan 2012 20:19:17 +0000 Subject: On AVX, we can load v8i32 at a time. The bug happens when two uneven loads are used. When we load the v12i32 type, the GenWidenVectorLoads method generates two loads: v8i32 and v4i32 and attempts to use CONCAT_VECTORS to join them. In this fix I concat undef values to widen the smaller value. The test "widen_load-2.ll" also exposes this bug on AVX. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147964 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/X86/2012-01-11-split-cv.ll | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 test/CodeGen/X86/2012-01-11-split-cv.ll (limited to 'test/CodeGen/X86/2012-01-11-split-cv.ll') diff --git a/test/CodeGen/X86/2012-01-11-split-cv.ll b/test/CodeGen/X86/2012-01-11-split-cv.ll new file mode 100644 index 0000000000..6b90072919 --- /dev/null +++ b/test/CodeGen/X86/2012-01-11-split-cv.ll @@ -0,0 +1,12 @@ +; RUN: llc < %s -march=x86 -mcpu=corei7-avx -mattr=+avx -mtriple=i686-pc-win32 | FileCheck %s + +;CHECK: add18i16 +define void @add18i16(<18 x i16>* nocapture sret %ret, <18 x i16>* %bp) nounwind { +;CHECK: vmovups + %b = load <18 x i16>* %bp, align 16 + %x = add <18 x i16> zeroinitializer, %b + store <18 x i16> %x, <18 x i16>* %ret, align 16 +;CHECK: ret + ret void +} + -- cgit v1.2.3