From c19d1c3ba2b216f0f91d71cf6fc2e983fc995854 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Sun, 19 Dec 2010 22:08:31 +0000 Subject: improve the setcc -> setcc_carry optimization to happen more consistently by moving it out of lowering into dag combine. Add some missing patterns for matching away extended versions of setcc_c. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122201 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/X86/add-of-carry.ll | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) (limited to 'test/CodeGen/X86/add-of-carry.ll') diff --git a/test/CodeGen/X86/add-of-carry.ll b/test/CodeGen/X86/add-of-carry.ll index 4c2257494d..f924ec8132 100644 --- a/test/CodeGen/X86/add-of-carry.ll +++ b/test/CodeGen/X86/add-of-carry.ll @@ -1,8 +1,9 @@ ; RUN: llc < %s -march=x86 | FileCheck %s ; -define i32 @add32carry(i32 %sum, i32 %x) nounwind readnone ssp { +define i32 @test1(i32 %sum, i32 %x) nounwind readnone ssp { entry: +; CHECK: test1: ; CHECK: sbbl %ecx, %ecx ; CHECK-NOT: addl ; CHECK: subl %ecx, %eax @@ -12,3 +13,22 @@ entry: %z.0 = add i32 %add4, %inc ret i32 %z.0 } + +; Instcombine transforms test1 into test2: +; CHECK: test2: +; CHECK: movl +; CHECK-NEXT: addl +; CHECK-NEXT: sbbl +; CHECK-NEXT: subl +; CHECK-NEXT: ret +define i32 @test2(i32 %sum, i32 %x) nounwind readnone ssp { +entry: + %uadd = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %x, i32 %sum) + %0 = extractvalue { i32, i1 } %uadd, 0 + %cmp = extractvalue { i32, i1 } %uadd, 1 + %inc = zext i1 %cmp to i32 + %z.0 = add i32 %0, %inc + ret i32 %z.0 +} + +declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32) nounwind readnone -- cgit v1.2.3