From 87070fe1073b1e95748d987af0810d02aac43603 Mon Sep 17 00:00:00 2001
From: Elena Demikhovsky <elena.demikhovsky@intel.com>
Date: Wed, 26 Jun 2013 10:55:03 +0000
Subject: Optimized integer vector multiplication operation by replacing it
 with shift/xor/sub when it is possible. Fixed a bug in SDIV, where the const
 operand is not a splat constant vector.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184931 91177308-0d34-0410-b5e6-96231b3b80d8
---
 test/CodeGen/X86/avx-shift.ll | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'test/CodeGen/X86/avx-shift.ll')

diff --git a/test/CodeGen/X86/avx-shift.ll b/test/CodeGen/X86/avx-shift.ll
index 01eb7361e2..d79dfcc076 100644
--- a/test/CodeGen/X86/avx-shift.ll
+++ b/test/CodeGen/X86/avx-shift.ll
@@ -103,9 +103,10 @@ define <32 x i8> @vshift12(<32 x i8> %a) nounwind readnone {
 
 ;;; Support variable shifts
 ; CHECK: _vshift08
-; CHECK: vextractf128 $1
 ; CHECK: vpslld $23
+; CHECK: vextractf128 $1
 ; CHECK: vpslld $23
+; CHECK: ret
 define <8 x i32> @vshift08(<8 x i32> %a) nounwind {
   %bitop = shl <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, %a
   ret <8 x i32> %bitop
-- 
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