From 1d82537762a0f4019bde301d498d190140585f57 Mon Sep 17 00:00:00 2001 From: Lang Hames Date: Mon, 21 Oct 2013 17:51:24 +0000 Subject: X86 vector element shift-by-immediate instructions take i8 immediates. Make the instruction defenitions and ISEL reflect this. Prior to this patch these instructions took an i32i8imm, and the high bits were dropped during encoding. This led to incorrect behavior for shifts by immediates higher than 255. This patch fixes that issue by detecting large immediate shifts and returning constant zero (for logical shifts) or capping the shift amount at an encodable value (for arithmetic shifts). Fixes git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193096 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/X86/avx2-vector-shifts.ll | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'test/CodeGen/X86/avx2-vector-shifts.ll') diff --git a/test/CodeGen/X86/avx2-vector-shifts.ll b/test/CodeGen/X86/avx2-vector-shifts.ll index a978d93fc5..5592e6c8a5 100644 --- a/test/CodeGen/X86/avx2-vector-shifts.ll +++ b/test/CodeGen/X86/avx2-vector-shifts.ll @@ -121,7 +121,7 @@ entry: } ; CHECK-LABEL: test_sraw_3: -; CHECK: vpsraw $16, %ymm0, %ymm0 +; CHECK: vpsraw $15, %ymm0, %ymm0 ; CHECK: ret define <8 x i32> @test_srad_1(<8 x i32> %InVec) { @@ -151,7 +151,7 @@ entry: } ; CHECK-LABEL: test_srad_3: -; CHECK: vpsrad $32, %ymm0, %ymm0 +; CHECK: vpsrad $31, %ymm0, %ymm0 ; CHECK: ret ; SSE Logical Shift Right -- cgit v1.2.3