From 7782102c70fdfd48776f05099eb67dd268cfc222 Mon Sep 17 00:00:00 2001 From: Chandler Carruth Date: Sat, 24 Dec 2011 12:12:34 +0000 Subject: Use standard promotion for i8 CTTZ nodes and i8 CTLZ nodes when the LZCNT instructions are available. Force promotion to i32 to get a smaller encoding since the fix-ups necessary are just as complex for either promoted type We can't do standard promotion for CTLZ when lowering through BSR because it results in poor code surrounding the 'xor' at the end of this instruction. Essentially, if we promote the entire CTLZ node to i32, we end up doing the xor on a 32-bit CTLZ implementation, and then subtracting appropriately to get back to an i8 value. Instead, our custom logic just uses the knowledge of the incoming size to compute a perfect xor. I'd love to know of a way to fix this, but so far I'm drawing a blank. I suspect the legalizer could be more clever and/or it could collude with the DAG combiner, but how... ;] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147251 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/X86/bmi.ll | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'test/CodeGen/X86/bmi.ll') diff --git a/test/CodeGen/X86/bmi.ll b/test/CodeGen/X86/bmi.ll index e79c92f1e2..43c47c0fa8 100644 --- a/test/CodeGen/X86/bmi.ll +++ b/test/CodeGen/X86/bmi.ll @@ -9,7 +9,7 @@ define i8 @t1(i8 %x) nounwind { %tmp = tail call i8 @llvm.cttz.i8( i8 %x, i1 false ) ret i8 %tmp ; CHECK: t1: -; CHECK: tzcntw +; CHECK: tzcntl } define i16 @t2(i16 %x) nounwind { @@ -37,7 +37,7 @@ define i8 @t5(i8 %x) nounwind { %tmp = tail call i8 @llvm.cttz.i8( i8 %x, i1 true ) ret i8 %tmp ; CHECK: t5: -; CHECK: tzcntw +; CHECK: tzcntl } define i16 @t6(i16 %x) nounwind { -- cgit v1.2.3