From f31408d75c42f48041e40aaaee147dcaa8477bc0 Mon Sep 17 00:00:00 2001 From: Dan Gohman Date: Tue, 13 Jan 2009 23:23:30 +0000 Subject: Disable the register+memory forms of the bt instructions for now. Thanks to Eli for pointing out that these forms don't ignore the high bits of their index operands, and as such are not immediately suitable for use by isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62194 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/X86/bt.ll | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'test/CodeGen/X86/bt.ll') diff --git a/test/CodeGen/X86/bt.ll b/test/CodeGen/X86/bt.ll index b63a3f8ecf..86254d3295 100644 --- a/test/CodeGen/X86/bt.ll +++ b/test/CodeGen/X86/bt.ll @@ -1,7 +1,12 @@ ; RUN: llvm-as < %s | llc | grep btl -; RUN: llvm-as < %s | llc -mcpu=pentium4 | grep btl | grep esp +; RUN: llvm-as < %s | llc -mcpu=pentium4 | grep btl | not grep esp ; RUN: llvm-as < %s | llc -mcpu=penryn | grep btl | not grep esp ; PR3253 + +; The register+memory form of the BT instruction should be usable on +; pentium4, however it is currently disabled due to the register+memory +; form having different semantics than the register+register form. + target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target triple = "i386-apple-darwin8" -- cgit v1.2.3