From 73c2f7f5ed767a6fc062fd198551be902b7b7d5b Mon Sep 17 00:00:00 2001 From: Manman Ren Date: Fri, 1 Jun 2012 19:49:33 +0000 Subject: X86: peephole optimization to remove cmp instruction This patch will optimize the following: sub r1, r3 cmp r3, r1 or cmp r1, r3 bge L1 TO sub r1, r3 bge L1 or ble L1 If the branch instruction can use flag from "sub", then we can eliminate the "cmp" instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157831 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/X86/jump_sign.ll | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'test/CodeGen/X86/jump_sign.ll') diff --git a/test/CodeGen/X86/jump_sign.ll b/test/CodeGen/X86/jump_sign.ll index cf5408e071..c1fad43fe5 100644 --- a/test/CodeGen/X86/jump_sign.ll +++ b/test/CodeGen/X86/jump_sign.ll @@ -83,6 +83,25 @@ entry: %cond = select i1 %cmp, i32 %sub, i32 0 ret i32 %cond } +; redundant cmp instruction +define i32 @l(i32 %a, i32 %b) nounwind { +entry: +; CHECK: l: +; CHECK-NOT: cmp + %cmp = icmp slt i32 %b, %a + %sub = sub nsw i32 %a, %b + %cond = select i1 %cmp, i32 %sub, i32 %a + ret i32 %cond +} +define i32 @m(i32 %a, i32 %b) nounwind { +entry: +; CHECK: m: +; CHECK-NOT: cmp + %cmp = icmp sgt i32 %a, %b + %sub = sub nsw i32 %a, %b + %cond = select i1 %cmp, i32 %b, i32 %sub + ret i32 %cond +} ; rdar://11540023 define i64 @n(i64 %x, i64 %y) nounwind { entry: -- cgit v1.2.3