From 32ecfb41585d377c25c30aa4260cf007c1b0d5ce Mon Sep 17 00:00:00 2001 From: Pete Cooper Date: Mon, 30 Jul 2012 20:23:19 +0000 Subject: Consider address spaces for hashing and CSEing DAG nodes. Otherwise two loads from different x86 segments but the same address would get CSEd git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160987 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/X86/movgs.ll | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'test/CodeGen/X86/movgs.ll') diff --git a/test/CodeGen/X86/movgs.ll b/test/CodeGen/X86/movgs.ll index aeb540fe42..65ee7b1d8e 100644 --- a/test/CodeGen/X86/movgs.ll +++ b/test/CodeGen/X86/movgs.ll @@ -55,4 +55,20 @@ entry: ; X64: ret } +; The two loads here both look identical to selection DAG, except for their +; address spaces. Make sure they aren't CSE'd. +define i32 @test_no_cse() nounwind readonly { +entry: + %tmp = load i32* addrspace(256)* getelementptr (i32* addrspace(256)* inttoptr (i32 72 to i32* addrspace(256)*), i32 31) ; [#uses=1] + %tmp1 = load i32* %tmp ; [#uses=1] + %tmp2 = load i32* addrspace(257)* getelementptr (i32* addrspace(257)* inttoptr (i32 72 to i32* addrspace(257)*), i32 31) ; [#uses=1] + %tmp3 = load i32* %tmp2 ; [#uses=1] + %tmp4 = add i32 %tmp1, %tmp3 + ret i32 %tmp4 +} +; X32: test_no_cse: +; X32: movl %gs:196 +; X32: movl %fs:196 +; X32: ret + declare <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16>) nounwind readnone -- cgit v1.2.3