From dbf8b5be977b79a7abd6bbdc38561b3a5164d195 Mon Sep 17 00:00:00 2001 From: Michael Liao Date: Tue, 28 Aug 2012 03:34:40 +0000 Subject: Fix PR12312 - Add a target-specific DAG optimization to recognize a pattern PTEST-able. Such a pattern is a OR'd tree with X86ISD::OR as the root node. When X86ISD::OR node has only its flag result being used as a boolean value and all its leaves are extracted from the same vector, it could be folded into an X86ISD::PTEST node. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162735 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/X86/pr12312.ll | 48 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 test/CodeGen/X86/pr12312.ll (limited to 'test/CodeGen/X86/pr12312.ll') diff --git a/test/CodeGen/X86/pr12312.ll b/test/CodeGen/X86/pr12312.ll new file mode 100644 index 0000000000..74733acc61 --- /dev/null +++ b/test/CodeGen/X86/pr12312.ll @@ -0,0 +1,48 @@ +; RUN: llc -march=x86-64 -mattr=+sse41,-avx < %s | FileCheck %s --check-prefix SSE41 +; RUN: llc -march=x86-64 -mattr=+avx < %s | FileCheck %s --check-prefix AVX + +define i32 @veccond(<4 x i32> %input) { +entry: + %0 = bitcast <4 x i32> %input to i128 + %1 = icmp ne i128 %0, 0 + br i1 %1, label %if-true-block, label %endif-block + +if-true-block: ; preds = %entry + ret i32 0 +endif-block: ; preds = %entry, + ret i32 1 +; SSE41: veccond +; SSE41: ptest +; SSE41: ret +; AVX: veccond +; AVX: vptest +; AVX: ret +} + +define i32 @vectest(<4 x i32> %input) { +entry: + %0 = bitcast <4 x i32> %input to i128 + %1 = icmp ne i128 %0, 0 + %2 = zext i1 %1 to i32 + ret i32 %2 +; SSE41: vectest +; SSE41: ptest +; SSE41: ret +; AVX: vectest +; AVX: vptest +; AVX: ret +} + +define i32 @vecsel(<4 x i32> %input, i32 %a, i32 %b) { +entry: + %0 = bitcast <4 x i32> %input to i128 + %1 = icmp ne i128 %0, 0 + %2 = select i1 %1, i32 %a, i32 %b + ret i32 %2 +; SSE41: vecsel +; SSE41: ptest +; SSE41: ret +; AVX: vecsel +; AVX: vptest +; AVX: ret +} -- cgit v1.2.3