From 42317ccb5fed9de14118e1c48417b814d94e3d28 Mon Sep 17 00:00:00 2001 From: Michael Liao Date: Wed, 20 Mar 2013 02:33:21 +0000 Subject: Fix PR15296 - Move SRA/SRL/SHL lowering support from DAG combination to DAG lowering to support extended 256-bit integer in AVX but not AVX2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177478 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/X86/pr15296.ll | 46 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 test/CodeGen/X86/pr15296.ll (limited to 'test/CodeGen/X86/pr15296.ll') diff --git a/test/CodeGen/X86/pr15296.ll b/test/CodeGen/X86/pr15296.ll new file mode 100644 index 0000000000..1187d80cdf --- /dev/null +++ b/test/CodeGen/X86/pr15296.ll @@ -0,0 +1,46 @@ +; RUN: llc < %s -mtriple=i686-pc-linux -mcpu=corei7-avx | FileCheck %s + +define <8 x i32> @shiftInput___vyuunu(<8 x i32> %input, i32 %shiftval, <8 x i32> %__mask) nounwind { +allocas: + %smear.0 = insertelement <8 x i32> undef, i32 %shiftval, i32 0 + %smear.1 = insertelement <8 x i32> %smear.0, i32 %shiftval, i32 1 + %smear.2 = insertelement <8 x i32> %smear.1, i32 %shiftval, i32 2 + %smear.3 = insertelement <8 x i32> %smear.2, i32 %shiftval, i32 3 + %smear.4 = insertelement <8 x i32> %smear.3, i32 %shiftval, i32 4 + %smear.5 = insertelement <8 x i32> %smear.4, i32 %shiftval, i32 5 + %smear.6 = insertelement <8 x i32> %smear.5, i32 %shiftval, i32 6 + %smear.7 = insertelement <8 x i32> %smear.6, i32 %shiftval, i32 7 + %bitop = lshr <8 x i32> %input, %smear.7 + ret <8 x i32> %bitop +} + +; CHECK: shiftInput___vyuunu +; CHECK: psrld +; CHECK: psrld +; CHECK: ret + +define <8 x i32> @shiftInput___canonical(<8 x i32> %input, i32 %shiftval, <8 x i32> %__mask) nounwind { +allocas: + %smear.0 = insertelement <8 x i32> undef, i32 %shiftval, i32 0 + %smear.7 = shufflevector <8 x i32> %smear.0, <8 x i32> undef, <8 x i32> zeroinitializer + %bitop = lshr <8 x i32> %input, %smear.7 + ret <8 x i32> %bitop +} + +; CHECK: shiftInput___canonical +; CHECK: psrld +; CHECK: psrld +; CHECK: ret + +define <4 x i64> @shiftInput___64in32bitmode(<4 x i64> %input, i64 %shiftval, <4 x i64> %__mask) nounwind { +allocas: + %smear.0 = insertelement <4 x i64> undef, i64 %shiftval, i32 0 + %smear.7 = shufflevector <4 x i64> %smear.0, <4 x i64> undef, <4 x i32> zeroinitializer + %bitop = lshr <4 x i64> %input, %smear.7 + ret <4 x i64> %bitop +} + +; CHECK: shiftInput___64in32bitmode +; CHECK: psrlq +; CHECK: psrlq +; CHECK: ret -- cgit v1.2.3