From d36076e4a3a57f55c044cd1cf21a39abe1edf2de Mon Sep 17 00:00:00 2001
From: Evan Cheng <evan.cheng@apple.com>
Date: Sun, 18 Oct 2009 19:57:27 +0000
Subject: Turn on post-alloc scheduling for x86.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84431 91177308-0d34-0410-b5e6-96231b3b80d8
---
 test/CodeGen/X86/sse3.ll | 22 +++++-----------------
 1 file changed, 5 insertions(+), 17 deletions(-)

(limited to 'test/CodeGen/X86/sse3.ll')

diff --git a/test/CodeGen/X86/sse3.ll b/test/CodeGen/X86/sse3.ll
index 703635c0f5..6319cb887a 100644
--- a/test/CodeGen/X86/sse3.ll
+++ b/test/CodeGen/X86/sse3.ll
@@ -17,8 +17,8 @@ entry:
         
 ; X64: t0:
 ; X64: 	movddup	(%rsi), %xmm0
-; X64:  pshuflw	$0, %xmm0, %xmm0
 ; X64:	xorl	%eax, %eax
+; X64:  pshuflw	$0, %xmm0, %xmm0
 ; X64:	pinsrw	$0, %eax, %xmm0
 ; X64:	movaps	%xmm0, (%rdi)
 ; X64:	ret
@@ -167,18 +167,12 @@ define internal void @t10() nounwind {
         store <4 x i16> %6, <4 x i16>* @g2, align 8
         ret void
 ; X64: 	t10:
-; X64: 		movq	_g1@GOTPCREL(%rip), %rax
-; X64: 		movaps	(%rax), %xmm0
 ; X64: 		pextrw	$4, %xmm0, %eax
-; X64: 		movaps	%xmm0, %xmm1
+; X64: 		pextrw	$6, %xmm0, %edx
 ; X64: 		movlhps	%xmm1, %xmm1
 ; X64: 		pshuflw	$8, %xmm1, %xmm1
 ; X64: 		pinsrw	$2, %eax, %xmm1
-; X64: 		pextrw	$6, %xmm0, %eax
-; X64: 		pinsrw	$3, %eax, %xmm1
-; X64: 		movq	_g2@GOTPCREL(%rip), %rax
-; X64: 		movq	%xmm1, (%rax)
-; X64: 		ret
+; X64: 		pinsrw	$3, %edx, %xmm1
 }
 
 
@@ -189,8 +183,8 @@ entry:
 	ret <8 x i16> %tmp7
 
 ; X64: t11:
-; X64:	movd	%xmm1, %eax
 ; X64:	movlhps	%xmm0, %xmm0
+; X64:	movd	%xmm1, %eax
 ; X64:	pshuflw	$1, %xmm0, %xmm0
 ; X64:	pinsrw	$1, %eax, %xmm0
 ; X64:	ret
@@ -203,8 +197,8 @@ entry:
 	ret <8 x i16> %tmp9
 
 ; X64: t12:
-; X64: 	pextrw	$3, %xmm1, %eax
 ; X64: 	movlhps	%xmm0, %xmm0
+; X64: 	pextrw	$3, %xmm1, %eax
 ; X64: 	pshufhw	$3, %xmm0, %xmm0
 ; X64: 	pinsrw	$5, %eax, %xmm0
 ; X64: 	ret
@@ -256,18 +250,12 @@ entry:
         %tmp9 = shufflevector <16 x i8> %tmp8, <16 x i8> %T0,  <16 x i32> < i32 0, i32 1, i32 2, i32 17,  i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef >
         ret <16 x i8> %tmp9
 ; X64: 	t16:
-; X64: 		movaps	LCPI17_0(%rip), %xmm1
-; X64: 		movd	%xmm1, %eax
 ; X64: 		pinsrw	$0, %eax, %xmm1
 ; X64: 		pextrw	$8, %xmm0, %eax
 ; X64: 		pinsrw	$1, %eax, %xmm1
 ; X64: 		pextrw	$1, %xmm1, %ecx
 ; X64: 		movd	%xmm1, %edx
 ; X64: 		pinsrw	$0, %edx, %xmm1
-; X64: 		movzbl	%cl, %ecx
-; X64: 		andw	$-256, %ax
-; X64: 		orw	%cx, %ax
-; X64: 		movaps	%xmm1, %xmm0
 ; X64: 		pinsrw	$1, %eax, %xmm0
 ; X64: 		ret
 }
-- 
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