From 1bd15700a0eb3057d3e2d65070c3fc6b99e0d8a2 Mon Sep 17 00:00:00 2001
From: Nick Lewycky <nicholas@mxc.ca>
Date: Mon, 20 Jun 2011 18:33:26 +0000
Subject: Emit movq for 64-bit register to XMM register moves, but continue to
 accept movd when assembling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133452 91177308-0d34-0410-b5e6-96231b3b80d8
---
 test/CodeGen/X86/bitcast2.ll       | 20 +++++++++++++++++++-
 test/CodeGen/X86/vec_set-8.ll      |  2 +-
 test/CodeGen/X86/vec_set-9.ll      |  2 +-
 test/CodeGen/X86/vec_set-C.ll      |  2 +-
 test/CodeGen/X86/vec_shuffle-14.ll |  4 ++--
 test/CodeGen/X86/vec_shuffle-17.ll |  2 +-
 6 files changed, 25 insertions(+), 7 deletions(-)

(limited to 'test/CodeGen/X86')

diff --git a/test/CodeGen/X86/bitcast2.ll b/test/CodeGen/X86/bitcast2.ll
index 48922b5f5a..71ecedf8f1 100644
--- a/test/CodeGen/X86/bitcast2.ll
+++ b/test/CodeGen/X86/bitcast2.ll
@@ -1,13 +1,31 @@
-; RUN: llc < %s -march=x86-64 | grep movd | count 2
+; RUN: llc < %s -march=x86-64 | FileCheck %s
 ; RUN: llc < %s -march=x86-64 | not grep rsp
 
 define i64 @test1(double %A) {
+; CHECK: test1
+; CHECK: movq
    %B = bitcast double %A to i64
    ret i64 %B
 }
 
 define double @test2(i64 %A) {
+; CHECK: test2
+; CHECK: movq
    %B = bitcast i64 %A to double
    ret double %B
 }
 
+define i32 @test3(float %A) {
+; CHECK: test3
+; CHECK: movd
+   %B = bitcast float %A to i32
+   ret i32 %B
+}
+
+define float @test4(i32 %A) {
+; CHECK: test4
+; CHECK: movd
+   %B = bitcast i32 %A to float
+   ret float %B
+}
+
diff --git a/test/CodeGen/X86/vec_set-8.ll b/test/CodeGen/X86/vec_set-8.ll
index 66056d0add..aaf66adb09 100644
--- a/test/CodeGen/X86/vec_set-8.ll
+++ b/test/CodeGen/X86/vec_set-8.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s
 ; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s
 ; CHECK-NOT: movsd
-; CHECK: movd {{%rdi|%rcx}}, %xmm0
+; CHECK: movq {{%rdi|%rcx}}, %xmm0
 ; CHECK-NOT: movsd
 
 define <2 x i64> @test(i64 %i) nounwind  {
diff --git a/test/CodeGen/X86/vec_set-9.ll b/test/CodeGen/X86/vec_set-9.ll
index 3656e5f6ca..aaa3184cf3 100644
--- a/test/CodeGen/X86/vec_set-9.ll
+++ b/test/CodeGen/X86/vec_set-9.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86-64 | grep movd | count 1
+; RUN: llc < %s -march=x86-64 | grep movq | count 1
 ; RUN: llc < %s -march=x86-64 | grep {movlhps.*%xmm0, %xmm0}
 
 define <2 x i64> @test3(i64 %A) nounwind {
diff --git a/test/CodeGen/X86/vec_set-C.ll b/test/CodeGen/X86/vec_set-C.ll
index 7636ac3b37..0cf308c235 100644
--- a/test/CodeGen/X86/vec_set-C.ll
+++ b/test/CodeGen/X86/vec_set-C.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movq
 ; RUN: llc < %s -march=x86 -mattr=+sse2 | grep mov | count 1
-; RUN: llc < %s -march=x86-64 -mattr=+sse2 | grep movd
+; RUN: llc < %s -march=x86-64 -mattr=+sse2 | grep movq
 
 define <2 x i64> @t1(i64 %x) nounwind  {
 	%tmp8 = insertelement <2 x i64> zeroinitializer, i64 %x, i32 0
diff --git a/test/CodeGen/X86/vec_shuffle-14.ll b/test/CodeGen/X86/vec_shuffle-14.ll
index f0cfc44ab1..a40f361a0c 100644
--- a/test/CodeGen/X86/vec_shuffle-14.ll
+++ b/test/CodeGen/X86/vec_shuffle-14.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=x86 -mattr=+sse2
 ; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movd | count 1
-; RUN: llc < %s -march=x86-64 -mattr=+sse2 | grep movd | count 2
-; RUN: llc < %s -march=x86-64 -mattr=+sse2 | grep movq | count 3
+; RUN: llc < %s -march=x86-64 -mattr=+sse2 | grep movd | count 1
+; RUN: llc < %s -march=x86-64 -mattr=+sse2 | grep movq | count 4
 ; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep xor
 
 define <4 x i32> @t1(i32 %a) nounwind  {
diff --git a/test/CodeGen/X86/vec_shuffle-17.ll b/test/CodeGen/X86/vec_shuffle-17.ll
index ebc8c5b34a..e174c2a8ac 100644
--- a/test/CodeGen/X86/vec_shuffle-17.ll
+++ b/test/CodeGen/X86/vec_shuffle-17.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s
 ; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s
 ; CHECK-NOT: xor
-; CHECK: movd {{%rdi|%rcx}}, %xmm0
+; CHECK: movq {{%rdi|%rcx}}, %xmm0
 ; CHECK-NOT: xor
 ; PR2108
 
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