From 3b370a2ac433c4abfbfe8f47c63fee0dbcfcc9e6 Mon Sep 17 00:00:00 2001 From: Chad Rosier Date: Thu, 17 Oct 2013 18:12:29 +0000 Subject: [AArch64] Add support for NEON scalar three register different instruction class. The instruction class includes the signed saturating doubling multiply-add long, signed saturating doubling multiply-subtract long, and the signed saturating doubling multiply long instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192908 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/AArch64/neon-scalar-mul.ll | 75 +++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) (limited to 'test/CodeGen') diff --git a/test/CodeGen/AArch64/neon-scalar-mul.ll b/test/CodeGen/AArch64/neon-scalar-mul.ll index 6914a08135..3129df20f0 100644 --- a/test/CodeGen/AArch64/neon-scalar-mul.ll +++ b/test/CodeGen/AArch64/neon-scalar-mul.ll @@ -68,3 +68,78 @@ define double @test_vmulxd_f64(double %a, double %b) { declare <1 x float> @llvm.aarch64.neon.vmulx.v1f32(<1 x float>, <1 x float>) declare <1 x double> @llvm.aarch64.neon.vmulx.v1f64(<1 x double>, <1 x double>) + +define i32 @test_vqdmlalh_s16(i16 %a, i16 %b) { +; CHECK: test_vqdmlalh_s16 +; CHECK: sqdmlal {{s[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}} +entry: + %vqdmlal.i = insertelement <1 x i16> undef, i16 %a, i32 0 + %vqdmlal1.i = insertelement <1 x i16> undef, i16 %b, i32 0 + %vqdmlal2.i = call <1 x i32> @llvm.aarch64.neon.vqdmlal.v1i32(<1 x i16> %vqdmlal.i, <1 x i16> %vqdmlal1.i) + %0 = extractelement <1 x i32> %vqdmlal2.i, i32 0 + ret i32 %0 +} + +define i64 @test_vqdmlals_s32(i32 %a, i32 %b) { +; CHECK: test_vqdmlals_s32 +; CHECK: sqdmlal {{d[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} +entry: + %vqdmlal.i = insertelement <1 x i32> undef, i32 %a, i32 0 + %vqdmlal1.i = insertelement <1 x i32> undef, i32 %b, i32 0 + %vqdmlal2.i = call <1 x i64> @llvm.aarch64.neon.vqdmlal.v1i64(<1 x i32> %vqdmlal.i, <1 x i32> %vqdmlal1.i) + %0 = extractelement <1 x i64> %vqdmlal2.i, i32 0 + ret i64 %0 +} + +declare <1 x i32> @llvm.aarch64.neon.vqdmlal.v1i32(<1 x i16>, <1 x i16>) +declare <1 x i64> @llvm.aarch64.neon.vqdmlal.v1i64(<1 x i32>, <1 x i32>) + +define i32 @test_vqdmlslh_s16(i16 %a, i16 %b) { +; CHECK: test_vqdmlslh_s16 +; CHECK: sqdmlsl {{s[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}} +entry: + %vqdmlsl.i = insertelement <1 x i16> undef, i16 %a, i32 0 + %vqdmlsl1.i = insertelement <1 x i16> undef, i16 %b, i32 0 + %vqdmlsl2.i = call <1 x i32> @llvm.aarch64.neon.vqdmlsl.v1i32(<1 x i16> %vqdmlsl.i, <1 x i16> %vqdmlsl1.i) + %0 = extractelement <1 x i32> %vqdmlsl2.i, i32 0 + ret i32 %0 +} + +define i64 @test_vqdmlsls_s32(i32 %a, i32 %b) { +; CHECK: test_vqdmlsls_s32 +; CHECK: sqdmlsl {{d[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} +entry: + %vqdmlsl.i = insertelement <1 x i32> undef, i32 %a, i32 0 + %vqdmlsl1.i = insertelement <1 x i32> undef, i32 %b, i32 0 + %vqdmlsl2.i = call <1 x i64> @llvm.aarch64.neon.vqdmlsl.v1i64(<1 x i32> %vqdmlsl.i, <1 x i32> %vqdmlsl1.i) + %0 = extractelement <1 x i64> %vqdmlsl2.i, i32 0 + ret i64 %0 +} + +declare <1 x i32> @llvm.aarch64.neon.vqdmlsl.v1i32(<1 x i16>, <1 x i16>) +declare <1 x i64> @llvm.aarch64.neon.vqdmlsl.v1i64(<1 x i32>, <1 x i32>) + +define i32 @test_vqdmullh_s16(i16 %a, i16 %b) { +; CHECK: test_vqdmullh_s16 +; CHECK: sqdmull {{s[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}} +entry: + %vqdmull.i = insertelement <1 x i16> undef, i16 %a, i32 0 + %vqdmull1.i = insertelement <1 x i16> undef, i16 %b, i32 0 + %vqdmull2.i = call <1 x i32> @llvm.aarch64.neon.vqdmull.v1i32(<1 x i16> %vqdmull.i, <1 x i16> %vqdmull1.i) + %0 = extractelement <1 x i32> %vqdmull2.i, i32 0 + ret i32 %0 +} + +define i64 @test_vqdmulls_s32(i32 %a, i32 %b) { +; CHECK: test_vqdmulls_s32 +; CHECK: sqdmull {{d[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} +entry: + %vqdmull.i = insertelement <1 x i32> undef, i32 %a, i32 0 + %vqdmull1.i = insertelement <1 x i32> undef, i32 %b, i32 0 + %vqdmull2.i = call <1 x i64> @llvm.aarch64.neon.vqdmull.v1i64(<1 x i32> %vqdmull.i, <1 x i32> %vqdmull1.i) + %0 = extractelement <1 x i64> %vqdmull2.i, i32 0 + ret i64 %0 +} + +declare <1 x i32> @llvm.aarch64.neon.vqdmull.v1i32(<1 x i16>, <1 x i16>) +declare <1 x i64> @llvm.aarch64.neon.vqdmull.v1i64(<1 x i32>, <1 x i32>) -- cgit v1.2.3