From aab6231cd910dcd40217bc9cf73bf72223f2cf30 Mon Sep 17 00:00:00 2001 From: Benjamin Kramer Date: Sat, 26 Apr 2014 12:06:28 +0000 Subject: DAGCombiner: Turn divs of vector splats into vectorized multiplications. Otherwise the legalizer would just scalarize everything. Support for mulhi in the targets isn't that great yet so on most targets we get exactly the same scalarized output. Add a test for x86 vector udiv. I had to disable the mulhi nodes on ARM because there aren't any patterns for it. As far as I know ARM has instructions for getting the high part of a multiply so this should be fixed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207315 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/X86/vector-idiv.ll | 45 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 test/CodeGen/X86/vector-idiv.ll (limited to 'test/CodeGen') diff --git a/test/CodeGen/X86/vector-idiv.ll b/test/CodeGen/X86/vector-idiv.ll new file mode 100644 index 0000000000..5b8153a968 --- /dev/null +++ b/test/CodeGen/X86/vector-idiv.ll @@ -0,0 +1,45 @@ +; RUN: llc -march=x86-64 -mcpu=core2 < %s | FileCheck %s -check-prefix=SSE +; RUN: llc -march=x86-64 -mcpu=core-avx2 < %s | FileCheck %s -check-prefix=AVX + +define <4 x i32> @test1(<4 x i32> %a) { + %div = udiv <4 x i32> %a, + ret <4 x i32> %div + +; SSE-LABEL: test1: +; SSE: pmuludq +; SSE: pshufd $57 +; SSE: pmuludq +; SSE: shufps $-35 +; SSE: psubd +; SSE: psrld $1 +; SSE: padd +; SSE: psrld $2 + +; AVX-LABEL: test1: +; AVX: vpmuludq +; AVX: vpshufd $57 +; AVX: vpmuludq +; AVX: vshufps $-35 +; AVX: vpsubd +; AVX: vpsrld $1 +; AVX: vpadd +; AVX: vpsrld $2 +} + +define <8 x i32> @test2(<8 x i32> %a) { + %div = udiv <8 x i32> %a, + ret <8 x i32> %div + +; AVX-LABEL: test2: +; AVX: vpermd +; AVX: vpmuludq +; AVX: vshufps $-35 +; AVX: vpmuludq +; AVX: vshufps $-35 +; AVX: vpsubd +; AVX: vpsrld $1 +; AVX: vpadd +; AVX: vpsrld $2 +} + +; TODO: sdiv -> pmuldq -- cgit v1.2.3