From a2fce1169d8696f9950a17b1f85126b08c863154 Mon Sep 17 00:00:00 2001 From: Saleem Abdulrasool Date: Sun, 12 Jan 2014 04:36:01 +0000 Subject: ARM: change implicit immediate forms of {ld,st}r{,b}t to psuedo-instructions The implicit immediate 0 forms are assembly aliases, not distinct instruction encodings. Fix the initial implementation introduced in r198914 to an alias to avoid two separate instruction definitions for the same encoding. An InstAlias is insufficient in this case as the necessary due to the need to add a new additional operand for the implicit zero. By using the AsmPsuedoInst, fall back to the C++ code to transform the instruction to the equivalent _POST_IMM form, inserting the additional implicit immediate 0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199032 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/MC/Disassembler/ARM/addrmode2-reencoding.txt | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'test/MC/Disassembler/ARM/addrmode2-reencoding.txt') diff --git a/test/MC/Disassembler/ARM/addrmode2-reencoding.txt b/test/MC/Disassembler/ARM/addrmode2-reencoding.txt index 128b4b971c..08d2de687a 100644 --- a/test/MC/Disassembler/ARM/addrmode2-reencoding.txt +++ b/test/MC/Disassembler/ARM/addrmode2-reencoding.txt @@ -5,8 +5,8 @@ 0x00 0x10 0xa0 0xe4 0x00 0x10 0xe0 0xe4 -# CHECK: ldrt r1, [r0] @ encoding: [0x00,0x10,0xb0,0xe4] -# CHECK: ldrbt r1, [r0] @ encoding: [0x00,0x10,0xf0,0xe4] -# CHECK: strt r1, [r0] @ encoding: [0x00,0x10,0xa0,0xe4] -# CHECK: strbt r1, [r0] @ encoding: [0x00,0x10,0xe0,0xe4] +# CHECK: ldrt r1, [r0], #0 @ encoding: [0x00,0x10,0xb0,0xe4] +# CHECK: ldrbt r1, [r0], #0 @ encoding: [0x00,0x10,0xf0,0xe4] +# CHECK: strt r1, [r0], #0 @ encoding: [0x00,0x10,0xa0,0xe4] +# CHECK: strbt r1, [r0], #0 @ encoding: [0x00,0x10,0xe0,0xe4] -- cgit v1.2.3